公开(公告)号：USRE46419E1

公开(公告)日：2017-05-30

申请号：US14282756

申请日：2014-05-20

Applicant: INTERSIL AMERICAS INC.

Inventor： Robert H. Isham ,  Weihong Qiu

IPC: G05F1/40

CPC classification number: H03K7/08 ,  H02M3/156 ,  H02M3/1584 ,  H03K7/04

Abstract: An adaptive pulse positioning modulator including a sense circuit which provides a compensation signal indicative of output voltage error, a filter circuit having an input receiving the compensation signal and an output providing an adjust signal, a leading ramp circuit which provides a repetitive first leading edge ramp signal having a slope which is adjusted by the adjust signal, a comparator circuit which provides a first start trigger signal when the first leading edge ramp signal reaches the compensation signal and a first end trigger signal when a first trailing edge ramp signal reaches the compensation signal, a trailing ramp circuit which initiates ramping of the first trailing edge ramp signal when the first start trigger signal is provided, and a pulse control logic which asserts pulses on a PWM signal based on the trigger signals.

公开(公告)号：US09165863B2

公开(公告)日：2015-10-20

申请号：US13932076

申请日：2013-07-01

Applicant: INTERSIL AMERICAS INC.

Inventor： Randolph Cruz

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/49548 ,  H01L21/4828 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49541 ,  H01L2224/32245

Abstract: Systems and methods for lead frame locking design features are provided. In one embodiment, a method comprises: fabricating a lead frame for a chip package, the lead frame having a paddle comprising a step-out bottom locking feature profile across at least a first segment of an edge of the paddle that provides an interface with a mold compound; etching the paddle to have at least a second segment of the edge having either an extended-step-out bottom locking feature profile or an overhanging top locking feature profile; and alternating first and second segments along the edge of the paddle.

Abstract translation: 提供了引线框锁定设计特点的系统和方法。 在一个实施例中，一种方法包括：制造用于芯片封装的引线框架，所述引线框架具有桨叶，所述桨叶包括横跨所述桨叶边缘的至少第一段的逐步底部锁定特征轮廓，其提供与 模具复合; 蚀刻所述桨叶以使所述边缘的至少第二段具有延伸出的底部锁定特征轮廓或悬垂顶部锁定特征轮廓; 以及沿桨叶的边缘交替的第一和第二段。

公开(公告)号：US20150030057A1

公开(公告)日：2015-01-29

申请号：US14513905

申请日：2014-10-14

Applicant: INTERSIL AMERICAS INC.

Inventor： Christopher Keith Davis ,  Jeffrey David Lies

IPC: H04L25/02

CPC classification number: H04L25/0276 ,  H04L25/0292

Abstract: Systems and methods for providing a full fail-safe capability in signal transmission networks are disclosed. For example, a system for providing a full fail-safe capability in signal transmission networks includes at least a first electronic circuit to transmit and receive signals or data, at least one driver unit coupled to the at least a first electronic circuit, and at least one receiver unit coupled to the at least a first electronic circuit and the at least one driver unit. The at least one receiver unit includes at least one offset signal generating unit, a signal comparing unit, and a switching unit to couple an offset signal from the at least one offset signal generating unit to an input of the signal comparing unit.

Abstract translation: 公开了用于在信号传输网络中提供完全故障安全能力的系统和方法。 例如，用于在信号传输网络中提供完整的故障安全能力的系统包括至少第一电子电路，用于发送和接收信号或数据，耦合到至少第一电子电路的至少一个驱动器单元，并且至少 耦合到所述至少第一电子电路和所述至少一个驱动器单元的一个接收器单元。 所述至少一个接收器单元包括至少一个偏移信号生成单元，信号比较单元和用于将来自所述至少一个偏移信号生成单元的偏移信号耦合到所述信号比较单元的输入的切换单元。

公开(公告)号：USRE45227E1

公开(公告)日：2014-11-04

申请号：US13683118

申请日：2012-11-21

Applicant: Intersil Americas, Inc.

Inventor： Sunder S. Kidambi

IPC: H03M1/06 ,  H04B1/16

CPC classification number: H03M1/06 ,  H03M1/0624 ,  H03M1/1028 ,  H03M1/1215 ,  H04B1/16

Abstract: A two-channel time-interleaved analog-to-digital converter (TIADC) system that provides for estimation and correction of offset, gain, and sample-time errors. Error in the offsets of the two ADCs that form the TIADC produces a spurious signal at the Nyquist frequency that can be used to minimize the difference of offsets of the ADCs. The difference in gain between the two ADCs produces spurious signals reflected around the Nyquist frequency whose magnitudes can be reduced by minimizing the difference in signal power between the two ADCs. An Automatic Gain Control loop corrects the scaling of the input signal due to the average of the gains of the ADCs. Phase error produces spurious signals reflected around the Nyquist frequency that are π/2 out of phase with those due to the gain error. Minimizing the difference between the correlation of consecutive signals from the ADCs reduces the magnitude of these image tones.

Abstract translation: 双通道时间交织模数转换器（TIADC）系统，提供偏移，增益和采样时间误差的估计和校正。 形成TIADC的两个ADC的偏移量误差会产生奈奎斯特频率处的寄生信号，可以将ADC的偏移差减到最小。 两个ADC之间的增益差异会产生在奈奎斯特频率周围反射的杂散信号，其幅度可以通过最小化两个ADC之间的信号功率差异来降低。 自动增益控制环路由于ADC的增益平均而校正输入信号的比例。 相位误差会产生与奈奎斯特频率反射的寄生信号，这些信号与由于增益误差引起的寄生信号相差/ 2相位差。 最小化来自ADC的连续信号的相关性之间的差异降低了这些图像色调的幅度。

公开(公告)号：US20140206300A1

公开(公告)日：2014-07-24

申请号：US14224595

申请日：2014-03-25

Applicant: Intersil Americas Inc.

Inventor： Wilhelm Steffen Hahn ,  Wei Chen

IPC: H04B15/00 ,  H04B1/44

CPC classification number: H04B15/00 ,  H04B1/44 ,  H04B1/52 ,  H04B1/525

Abstract: Signals propagating from an aggressor communication channel can cause detrimental interference in a victim communication channel. One or more noise cancellers can generate an interference compensation signal to suppress or cancel the interference based on one or more settings. A controller can execute algorithms to find preferred settings for the noise canceller(s). The controller can use a feedback signal (e.g., receive signal quality indicator) received from a victim receiver during the execution of the algorithm(s) to find the preferred settings. One exemplary algorithm includes sequentially evaluating the feedback resulting from a predetermined list of settings. Another algorithm includes determining whether to move from one setting to the next based on the feedback values for both settings. Yet another algorithm includes evaluating a number of sample settings to determine which of the sample settings result in a better feedback value and searching around that sample setting for a preferred setting.

Abstract translation: 从侵略者通信信道传播的信号可能对受害者通信信道造成有害的干扰。 一个或多个噪声消除器可以基于一个或多个设置产生干扰补偿信号以抑制或消除干扰。 控制器可以执行算法来找到噪声消除器的优选设置。 控制器可以在执行算法期间使用从受害者接收器接收到的反馈信号（例如，接收信号质量指示符）以找到优选设置。 一个示例性算法包括从预定的设置列表顺序地评估反馈。 另一种算法包括基于两个设置的反馈值确定是否从一个设置移动到下一个设置。 另一种算法包括评估多个样本设置，以确定哪个样本设置导致更好的反馈值，并围绕该样本设置搜索优选设置。

公开(公告)号：US08742738B2

公开(公告)日：2014-06-03

申请号：US13685513

申请日：2012-11-26

Applicant: Intersil Americas Inc.

Inventor： Michael Jason Houston

IPC: G05F1/00

CPC classification number: G05F1/10 ,  H02M3/156 ,  H02M3/1584

Abstract: A method and system control the adding or dropping of phases in a multiphase voltage regulator. The regulator has an efficiency and this efficiency of the regulator is calculated for a given number of phases being activated from an output voltage, input voltage, output current, and duty cycle of the regulator. The efficiency of the regulator is also calculated if a phase is added using the derivative of the duty cycle as a function of the output current. The efficiency of the regulator is further calculated if a phase is dropped using the derivative of the duty cycle as a function of the output current. From these operations of calculating, a phase is either added, dropped, or the phase is maintained at its current value to thereby optimize the efficiency of the regulator.

Abstract translation: 一种方法和系统控制多相电压调节器中的相位的增加或减少。 调节器具有效率，并且对于从输出电压，输入电压，输出电流和调节器的占空比激活的给定数量的相位来计算调节器的效率。 如果使用占空比的导数作为输出电流的函数来添加相位，则也可以计算调节器的效率。 如果使用占空比的导数作为输出电流的函数降低相位，则进一步计算调节器的效率。 从这些计算操作中，相位被添加，下降或相位保持在其当前值，从而优化调节器的效率。

公开(公告)号：US20130082670A1

公开(公告)日：2013-04-04

申请号：US13685513

申请日：2012-11-26

Applicant: INTERSIL AMERICAS INC.

Inventor： Michael Jason Houston

IPC: G05F1/10

CPC classification number: G05F1/10 ,  H02M3/156 ,  H02M3/1584

Abstract: A method and system control the adding or dropping of phases in a multiphase voltage regulator. The regulator has an efficiency and this efficiency of the regulator is calculated for a given number of phases being activated from an output voltage, input voltage, output current, and duty cycle of the regulator. The efficiency of the regulator is also calculated if a phase is added using the derivative of the duty cycle as a function of the output current. The efficiency of the regulator is further calculated if a phase is dropped using the derivative of the duty cycle as a function of the output current. From these operations of calculating, a phase is either added, dropped, or the phase is maintained at its current value to thereby optimize the efficiency of the regulator.

公开(公告)号：US20040212348A1

公开(公告)日：2004-10-28

申请号：US10850206

申请日：2004-05-20

Applicant: Intersil Americas Inc.

Inventor： Zheren Lai ,  Edward Bordeaux ,  Zen Wu

IPC: H02J007/00

CPC classification number: H02J7/0055 ,  H02J7/0073 ,  H02J7/0093

Abstract: A battery charger controller is coupled to DC output terminals of an AC-DC (or DC-DC) adapter containing an AC-DC (or DC-DC) converter. A controlled current flow path between input and output terminals of the battery charger controller circuit is controlled to provide a substantially constant current to charge the battery to a nominal battery voltage. When a constant voltage output of the said adapter transitions to a value that limits available charging current to a value less than programmed constant charging current, current flow drive for the controlled current flow path is increased for a limited time interval. Thereafter, the controlled current flow path gradually reduces charging current as the battery voltage remains at its nominal battery voltage until the charge is complete or otherwise terminated.

Abstract translation: 电池充电器控制器耦合到包含AC-DC（或DC-DC）转换器的AC-DC（或DC-DC）适配器的DC输出端子。 控制电池充电器控制器电路的输入和输出端子之间的受控电流流动路径以提供基本恒定的电流，以将电池充电至标称电池电压。 当所述适配器的恒定电压输出转换到将可用充电电流限制到小于编程的恒定充电电流的值的值时，受控电流流动路径的电流流动驱动在有限的时间间隔内增加。 此后，随着电池电压保持在其标称电池电压，直到充电完成或以其他方式终止，受控电流流路逐渐降低充电电流。

公开(公告)号：US20040178779A1

公开(公告)日：2004-09-16

申请号：US10806605

申请日：2004-03-23

Applicant: INTERSIL AMERICAS INC.

Inventor： Michael M. Walters ,  Matthew B. Harris ,  Bogdan M. Duduman

IPC: H02M003/24

CPC classification number: H02M3/1588 ,  H02M3/156 ,  H02M3/1584 ,  H02M3/285 ,  H02M2001/0009 ,  Y02B70/1466

Abstract: A DC-to-DC converter includes one or more power switches, a pulse width modulation circuit for generating control pulses for the power switches, and an output inductor connected to the power switches. A thermally compensated current sensor is connected to an intrinsic current sensing element exhibiting a temperature-based parameter non-linearity. The thermally compensated current sensor has a temperature coefficient that substantially matches a temperature coefficient of an intrinsic power converter element used to measure current flow, thus linearizing the current measurement. Also, a current feedback loop circuit cooperates with the pulse width modulation circuit to control the power switches responsive to the thermally compensated current sensor.

公开(公告)号：US20040160194A1

公开(公告)日：2004-08-19

申请号：US10777955

申请日：2004-02-12

Applicant: Intersil Americas Inc.

Inventor： Grady M. Wood

IPC: G09G003/10

CPC classification number: H05B33/08 ,  Y02B20/32

Abstract: An electroluminescent driver circuit with improved power consumption efficiency. In one embodiment, an electroluminescent driver circuit comprises a load to provide illumination, an inductor, a transistor and a plurality of switches. The inductor has a first side coupled to a positive terminal of a power supply and a second side selectively coupled to the load. The transistor is coupled to selectively conduct current from the second side of the inductor to a ground terminal of the power supply in response to a digital signal. The plurality of switches are coupled to the load to selectively charge and discharge the load. Moreover, the switches selectively provide a discharge path for positive charge on the load to be discharged to the positive terminal of the power supply.