Invention Application
US20020126563A1 INTERLEAVED MEMORY DEVICE FOR SEQUENTIAL ACCESS SYNCHRONOUS READING WITH SIMPLIFIED ADDRESS COUNTERS
有权
用于具有简化地址计数器的顺序访问同步读取的交互式存储器件
- Patent Title: INTERLEAVED MEMORY DEVICE FOR SEQUENTIAL ACCESS SYNCHRONOUS READING WITH SIMPLIFIED ADDRESS COUNTERS
- Patent Title (中): 用于具有简化地址计数器的顺序访问同步读取的交互式存储器件
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Application No.: US09774539Application Date: 2001-01-31
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Publication No.: US20020126563A1Publication Date: 2002-09-12
- Inventor: Carmelo Condemi , Fabrizio Campanale , Salvatore Nicosia , Francesco Tomaiuolo , Luca Giuseppe De Ambroggi , Promod Kumar
- Applicant: STMicroelectronics S.r.l.
- Applicant Address: IT Agrate Brianza
- Assignee: STMicroelectronics S.r.l.
- Current Assignee: STMicroelectronics S.r.l.
- Current Assignee Address: IT Agrate Brianza
- Priority: EP00830068.3 20000131; ITVA2000A000015 20000530
- Main IPC: G11C008/18
- IPC: G11C008/18

Abstract:
An interleaved memory includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells. The interleaved memory operates in a burst access mode. A first address counter is coupled to the first bank of memory cells, and an address register is coupled to the first address counter and to the second bank of memory cells. A timing circuit generates increment pulses to the first address counter so that a first random access asynchronous read cycle starts with the first bank of memory cells. A function of an address counter for the second bank of memory cells is being performed by coping contents of the first address counter to the address register.
Public/Granted literature
- US06452864B1 Interleaved memory device for sequential access synchronous reading with simplified address counters Public/Granted day:2002-09-17
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