公开(公告)号：US20020126563A1

公开(公告)日：2002-09-12

申请号：US09774539

申请日：2001-01-31

Applicant: STMicroelectronics S.r.l.

Inventor： Carmelo Condemi ,  Fabrizio Campanale ,  Salvatore Nicosia ,  Francesco Tomaiuolo ,  Luca Giuseppe De Ambroggi ,  Promod Kumar

IPC: G11C008/18

CPC classification number: G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/106 ,  G11C7/1069 ,  G11C8/04 ,  G11C8/12 ,  G11C8/18

Abstract: An interleaved memory includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells. The interleaved memory operates in a burst access mode. A first address counter is coupled to the first bank of memory cells, and an address register is coupled to the first address counter and to the second bank of memory cells. A timing circuit generates increment pulses to the first address counter so that a first random access asynchronous read cycle starts with the first bank of memory cells. A function of an address counter for the second bank of memory cells is being performed by coping contents of the first address counter to the address register.

Abstract translation: 交错存储器包括分成第一存储单元组和第二存储单元组的存储器单元阵列。 交错存储器以突发存取模式运行。 第一地址计数器耦合到第一存储单元组，并且地址寄存器耦合到第一地址计数器和第二存储单元组。 定时电路向第一地址计数器产生增量脉冲，使得第一随机存取异步读周期从第一存储单元组开始。 第二存储单元组的地址计数器的功能正在通过将第一地址计数器的内容与地址寄存器进行对应来执行。

公开(公告)号：US20040130953A1

公开(公告)日：2004-07-08

申请号：US10639240

申请日：2003-08-11

Applicant: STMicroelectronics S.r.l.

Inventor： Luca De Ambroggi ,  Carmelo Condemi

IPC: G11C007/00

CPC classification number: G11C29/789 ,  G11C16/344 ,  G11C29/82

Abstract: The nonvolatile storage device is made up of a memory array divided into a plurality of data-storage units and a plurality of redundancy-storage units for replacing respective failed data-storage units. A control unit detects the functionality of the data-storage units and, in case of failure, enables a redundancy-detection unit having a plurality of volatile-memory elements connected through a sequential daisy-chain connection. A nonvolatile memory unit stores, in a nonvolatile way, the redundancy information through a data bus, connected both to the redundancy-detection unit and to the nonvolatile memory unit; in the event of failure, the redundancy-detection unit transfers the addresses of the failed data-storage unit to the nonvolatile memory unit for their nonvolatile storage.

Abstract translation: 非易失性存储装置由划分成多个数据存储单元的存储器阵列和用于替换各个故障数据存储单元的多个冗余存储单元组成。 控制单元检测数据存储单元的功能，并且在故障的情况下，能够实现具有通过连续菊花链连接连接的多个易失性存储元件的冗余检测单元。 非易失性存储器单元通过数据总线以非易失性方式存储冗余信息，数据总线连接到冗余检测单元和非易失性存储器单元; 在故障的情况下，冗余检测单元将非易失性存储单元的故障数据存储单元的地址传送到非易失性存储单元。

公开(公告)号：US20010036244A1

公开(公告)日：2001-11-01

申请号：US09774878

申请日：2001-01-31

Applicant: STMicroelectronics S.r.l.

Inventor： Luca Giuseppe De Ambroggi ,  Salvatore Nicosia ,  Francesco Tomaiuolo ,  Fabrizio Campanale ,  Promod Kumar ,  Carmelo Condemi

IPC: G06M003/00

CPC classification number: G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

Abstract: An address binary counter for an interleaved having an array of memory cells being divided into a first bank of memory cells and a second bank of memory cells includes as many stages as the bits that may be stored in the memory cells of a row of one of the banks, and a carry calculation network. The interleaved memory operates in a burst access mode enabled by an enabling signal. The carry calculation network includes an ordered group of independent carry generators. Each independent carry generator includes a certain number of stages, with each stage having inputs receiving its own enabling bit and a number of consecutive bits of a row of the bank equal to the number of stages, orderly starting from the least significant bit. The enabling bit of the first carry generator of the ordered group is the enabling signal, and the enabling bit of any other carry generator of the ordered group is the logic AND of the enabling signal and of the input bits of the preceding carry generator of the ordered group.

Abstract translation: 用于交织的地址二进制计数器，其具有被划分为第一存储单元组和第二存储单元组的存储器单元的阵列，包括与存储在一行存储单元 银行和进位计算网络。 交织的存储器以启用信号启用的突发存取模式工作。 进位计算网络包括有序组的独立进位发生器。 每个独立进位发生器包括一定数量的级，其中每个级具有从最低有效位开始有序地接收其自身使能位和存储体的一行的连续位数等于级数的输入。 有序组的第一进位发生器的使能位是使能信号，有序组的任何其他进位发生器的使能位是使能信号和先前进位发生器的输入位的逻辑“与” 订购组。