Invention Application
US20020181826A1 Structure and method for fabricating a high-speed interface in semiconductor structures
审中-公开
用于在半导体结构中制造高速界面的结构和方法
- Patent Title: Structure and method for fabricating a high-speed interface in semiconductor structures
- Patent Title (中): 用于在半导体结构中制造高速界面的结构和方法
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Application No.: US09870832Application Date: 2001-06-01
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Publication No.: US20020181826A1Publication Date: 2002-12-05
- Inventor: Timothy Joe Johnson , Kevin B. Traylor , Duane C. Rabe
- Applicant: MOTOROLA, INC.
- Applicant Address: IL Schaumburg
- Assignee: MOTOROLA, INC.
- Current Assignee: MOTOROLA, INC.
- Current Assignee Address: IL Schaumburg
- Main IPC: G02B006/13
- IPC: G02B006/13

Abstract:
High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates by forming a compliant substrate for growing the monocrystalline layers. One way to achieve compliancy includes first growing on a silicon wafer an accommodating buffer layer that is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. In this way, high speed devices can be fabricated along with integral silicon-based circuitry to provide an efficient, low-cost semiconductor structure. Moreover, I/O pins and their associated problems can be eliminated.
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