公开(公告)号：US20020181826A1

公开(公告)日：2002-12-05

申请号：US09870832

申请日：2001-06-01

Applicant: MOTOROLA, INC.

Inventor： Timothy Joe Johnson ,  Kevin B. Traylor ,  Duane C. Rabe

IPC: G02B006/13

CPC classification number: H01L27/0605 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/02546 ,  H01L21/8258

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates by forming a compliant substrate for growing the monocrystalline layers. One way to achieve compliancy includes first growing on a silicon wafer an accommodating buffer layer that is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. In this way, high speed devices can be fabricated along with integral silicon-based circuitry to provide an efficient, low-cost semiconductor structure. Moreover, I/O pins and their associated problems can be eliminated.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长成覆盖在单晶衬底上。 实现符合性的一种方式包括首先在硅晶片上生长一个容纳缓冲层，该缓冲层是通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 以这种方式，可以与集成硅基电路一起制造高速器件，以提供有效的低成本半导体结构。 此外，可以消除I / O引脚及其相关问题。

公开(公告)号：US20020180050A1

公开(公告)日：2002-12-05

申请号：US09870589

申请日：2001-06-01

Applicant: MOTOROLA, INC.

Inventor： Barbara M. Foley ,  Duane C. Rabe ,  Kevin B. Traylor ,  Timothy Joe Johnson

IPC: H01L023/48 ,  H01L023/52 ,  H01L029/40

CPC classification number: H01L27/0605 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/8258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. A device structure for interacting with optical storage media is formed overlying the monocrystalline substrate. Portions or an entirety of the device structure can also overly the accomodating buffer layer, or the monocrystalline material layer.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 实现顺应性衬底的形成的一种方式包括首先在硅晶片上生长容纳缓冲层。 容纳缓冲层是通过氧化硅的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。 用于与光学存储介质相互作用的器件结构形成在单晶衬底上。 部分或整个器件结构也可以过度地覆盖住容纳缓冲层或单晶材料层。

公开(公告)号：US20020179926A1

公开(公告)日：2002-12-05

申请号：US09870592

申请日：2001-06-01

Applicant: MOTOROLA, INC.

Inventor： Barbara M. Foley ,  Duane C. Rabe ,  Kevin B. Traylor ,  Timothy Joe Johnson

IPC: H01L029/74

CPC classification number: G11B5/3103 ,  G11B5/10 ,  G11B11/10534 ,  G11B33/12 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. A device structure for interacting with magnetic storage media is formed overlying the monocrystalline substrate. Portions or an entirety of the device structure can also overly the accomodating buffer layer, or the monocrystalline material layer.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 实现顺应性衬底的形成的一种方式包括首先在硅晶片上生长容纳缓冲层。 容纳缓冲层是通过氧化硅的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。 在单晶衬底上形成用于与磁存储介质相互作用的器件结构。 部分或整个器件结构也可以过度地覆盖住容纳缓冲层或单晶材料层。

公开(公告)号：US20020181825A1

公开(公告)日：2002-12-05

申请号：US09870831

申请日：2001-06-01

Applicant: MOTOROLA, INC.

Inventor： Timothy Joe Johnson ,  Kevin B. Traylor ,  Duane C. Rabe ,  Barbara Foley Barenburg

IPC: G02B006/12

CPC classification number: G02B6/132 ,  G02B6/12004 ,  G02B6/43 ,  G02B2006/12107 ,  G02B2006/12169 ,  G06F1/105 ,  H01L21/8258 ,  H01L27/0605

Abstract: An integrated circuit that distributes its clock signals optically is provided. The integrated circuit may preferably include a plurality of digital CMOS circuits that communicate optically. The optical devices are preferably formed from compound semiconductor structures.

Abstract translation: 提供了一种以光学方式分配其时钟信号的集成电路。 集成电路可以优选地包括以光学方式通信的多个数字CMOS电路。 光学器件优选由化合物半导体结构形成。

公开(公告)号：US20020179930A1

公开(公告)日：2002-12-05

申请号：US09870835

申请日：2001-06-01

Applicant: MOTOROLA, INC.

Inventor： James S. Irwin ,  Clinton C. Powell ,  Timothy J. Johnson ,  Kevin B. Traylor ,  Duane C. Rabe ,  Barbara Foley Barenburg

IPC: H01L031/0328 ,  H01L031/0336 ,  H01L031/072 ,  H01L031/109

CPC classification number: G01R31/311

Abstract: A composite semiconductor structure includes islands of noncompound semiconductor materials formed on a noncompound substrate, and an optical testing structure. In one embodiment, a scan chain runs through the noncompound substrate (and possibly also through the islands) and terminates in the islands at optical interface elements, one of which is an optical emitter and the other of which is an optical detector. A test device inputs test signals to, and reads test signals from, the scan chain by interfacing optically with the optical interface elements. In another embodiment, an optical detector is formed in the silicon substrate and an optical emitter is formed in the compound semiconductor material. A leaky waveguide communicating with the emitter overlies the detector, and detection by the detector of light emitted by the emitter is an indication of the absence of an intended circuit element between the detector and the leaky side of the waveguide.

Abstract translation: 复合半导体结构包括形成在非复合衬底上的非复合半导体材料岛和光学测试结构。 在一个实施例中，扫描链穿过非复合衬底（并且可能还穿过岛）并终止在光学界面元件处的岛中，其中一个是光发射器，另一个是光学检测器。 测试设备通过与光学接口元件光学接口输入测试信号，并从扫描链中读取测试信号。 在另一个实施例中，在硅衬底中形成光学检测器，并且在化合物半导体材料中形成光发射器。 与发射器连通的泄漏波导覆盖在检测器上，并且由发射器发射的光的检测器的检测是在检测器和波导的泄漏侧之间不存在预期电路元件的指示。