Invention Application
US20020184547A1 Device and method for selectively powering down integrated circuit blocks within a system on chip
审中-公开
有选择地降低片上系统内的集成电路块的装置和方法
- Patent Title: Device and method for selectively powering down integrated circuit blocks within a system on chip
- Patent Title (中): 有选择地降低片上系统内的集成电路块的装置和方法
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Application No.: US10008586Application Date: 2001-11-05
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Publication No.: US20020184547A1Publication Date: 2002-12-05
- Inventor: Russell Francis , Michele Alia
- Applicant: STMicroelectronics S.r.I.
- Applicant Address: IT Agrate Brianza
- Assignee: STMicroelectronics S.r.I.
- Current Assignee: STMicroelectronics S.r.I.
- Current Assignee Address: IT Agrate Brianza
- Priority: EP00830732.4 20001103
- Main IPC: G06F001/26
- IPC: G06F001/26 ; G06F001/28 ; G06F001/30

Abstract:
A system-on-chip (SOC) includes a power down circuit. Within the SOC are several circuit blocks, each of them operating based upon a local clock signal. A system clock is coupled to each of the circuit blocks for providing a system clock signal thereto which functions as the local clock signal for selected circuit blocks. A power control manager provides a signal that at least partially determines whether the system clock signal will operate as the local clock signal for selected circuit blocks. The respective circuit blocks include a local power control circuit for selectively maintaining the system clock signal as the local clock signal after the local power control receives a signal from the power control manager to shutdown this circuit block if this circuit block is currently busy when the signal to shutdown is received.
Information query