Device and method for selectively powering down integrated circuit blocks within a system on chip
    1.
    发明申请
    Device and method for selectively powering down integrated circuit blocks within a system on chip 审中-公开
    有选择地降低片上系统内的集成电路块的装置和方法

    公开(公告)号:US20020184547A1

    公开(公告)日:2002-12-05

    申请号:US10008586

    申请日:2001-11-05

    Abstract: A system-on-chip (SOC) includes a power down circuit. Within the SOC are several circuit blocks, each of them operating based upon a local clock signal. A system clock is coupled to each of the circuit blocks for providing a system clock signal thereto which functions as the local clock signal for selected circuit blocks. A power control manager provides a signal that at least partially determines whether the system clock signal will operate as the local clock signal for selected circuit blocks. The respective circuit blocks include a local power control circuit for selectively maintaining the system clock signal as the local clock signal after the local power control receives a signal from the power control manager to shutdown this circuit block if this circuit block is currently busy when the signal to shutdown is received.

    Abstract translation: 片上系统(SOC)包括掉电电路。 SOC内有几个电路块,每个电路块基于本地时钟信号进行工作。 系统时钟耦合到每个电路块,以提供系统时钟信号,其用作所选电路块的本地时钟信号。 功率控制管理器提供至少部分地确定系统时钟信号是否将作为所选电路块的本地时钟信号工作的信号。 各个电路块包括本地电源控制电路,用于在本地功率控制接收到来自功率控制管理器的信号之后选择性地将系统时钟信号保持为本地时钟信号,以在该电路块当前正在忙时关闭该电路块 收到关机。

Patent Agency Ranking