Invention Application
US20020184547A1 Device and method for selectively powering down integrated circuit blocks within a system on chip 审中-公开
有选择地降低片上系统内的集成电路块的装置和方法

Device and method for selectively powering down integrated circuit blocks within a system on chip
Abstract:
A system-on-chip (SOC) includes a power down circuit. Within the SOC are several circuit blocks, each of them operating based upon a local clock signal. A system clock is coupled to each of the circuit blocks for providing a system clock signal thereto which functions as the local clock signal for selected circuit blocks. A power control manager provides a signal that at least partially determines whether the system clock signal will operate as the local clock signal for selected circuit blocks. The respective circuit blocks include a local power control circuit for selectively maintaining the system clock signal as the local clock signal after the local power control receives a signal from the power control manager to shutdown this circuit block if this circuit block is currently busy when the signal to shutdown is received.
Information query
Patent Agency Ranking
0/0