A memory cell for a two- or a three-dimensional memory array includes first and second conductors and set of layers situated between the conductors. This set of layers includes a dielectric rupture anti-fuse layer having a thickness less than 35 null and a leakage current density (in the unruptured state) greater than 1 mA/cm2 at 2 V. This low thickness and high current leakage density provide a memory cell with an asymmetric dielectric layer breakdown voltage characteristic. The antifuse layer is formed of an antifuse material characterized by a thickness Tminlife at which the antifuse material is ruptured by a minimum number of write pulses having a polarity that reverse biases diode components included in the memory cell. The average thickness T of the antifuse layer is less than the thickness Tminlife.