摘要:
A semiconductor memory device and method of reading data from the semiconductor memory device is described. The semiconductor memory device may generate a data read clock signal that changes from a first logic state to a second logic state, and may read out bit cell data from a plurality of bit lines based on the generated data read clock signal. A word line signal and a dummy word line signal may be activated from the first logic state to the second logic state based on incoming X-address signals and Y-address signals. An enable signal may be output based on the activated dummy word signal, and a sense amplifier may sense the read-out bit cell data and a reference signal based on the activated enable signal, and output a corresponding to the sensed read-out bit cell data.
摘要:
In a method for generating an identifier for an audio signal including a tone generated by an instrument, a discrete amplitude-time representation of the audio signal is generated at first, wherein the amplitude-time representation, for a plurality of subsequent points in time, comprises a plurality of subsequent amplitude values, wherein a point in time is associated to each amplitude value. Subsequently, an identifier for the audio signal is extracted from the amplitude-time representation. An instrument database is formed from several identifiers for several audio signals including tones of several instruments. By means of a test identifier for an audio signal having been produced by an unknown instrument, the type of the test instrument is determined using the instrument database. A precise instrument identification can be obtained by using the amplitude-time representation of a tone produced by an instrument for identifying a musical instrument.
摘要:
A water flushing system for a pressurized subterranean water distribution system includes an inlet conduit for receiving pressurized water from the subterranean water distribution system; an outlet fluidly connected to the inlet conduit for discharging pressurized water in the inlet conduit downwardly towards a drain; and a control valve for controlling the flow of pressurized water in the inlet conduit. The water flushing system further includes one or more of the following features: a freeze protection assembly, a detachable coupling system, a dechlorination system, and a backflow prevention system.
摘要:
A method for dynamically adjusting an operating speed of a microprocessor for the microprocessor to access at least a serial flash memory(together with a random access memory). The method includes reducing an executing speed of the microprocessor if the required data in the serial flash memory (or the random access memory) is not well prepared and executing the microprocessor at a normal speed if the required data in the serial flash memory(or the random access memory) is well prepared.
摘要:
The invention can provide a device, such as a semiconductor device, that accesses at least one semiconductor storage medium. The semiconductor device can include a given bus master that functions as a bus master, a bus interface that controls access to semiconductor storage media based on access request from the bus master, and a clock-supply-control circuit that controls the presence of the supply of a clock to the bus master based on access state information that indicates a state of access to the semiconductor storage media. The clock-supply-control circuit can stop the supply of the clock to the bus master if the bus interface is at a BUSY state, and supply the clock to the bus master if the bus interface is not at a BUSY state. Accordingly, a power consumption of a semiconductor device that accesses at least one semiconductor storage medium can be reduced.
摘要:
A semiconductor memory device including a main amplifier for amplifying an output from a bit line sensing amplifier and outputting the amplified output to a first data line; an input/output multiplexer connected to the first data line; a repeater connected to the first data line; an input/output write unit for receiving a data to be written and outputting the data to a second data line; and a write driver connected to the second data line for transferring the data on the second data line to the bit line sensing amplifier.
摘要:
A semiconductor memory device includes a first nonvolatile memory cell, a bit line connected to the first nonvolatile memory cell, and a control circuit connected to the first nonvolatile memory cell and the bit line, and disposed and configured in such a manner as to reset the bit line to a predetermined first potential state only for a certain period nullanull of time in response to transition of an input address signal. The first nonvolatile memory cell has a gate electrode formed on a semiconductor layer via a gate insulating film; a channel region disposed under the gate electrode; diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region; and memory functional units formed on both sides of the gate electrode and having the function of retaining charges.
摘要:
An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.
摘要:
The present invention is directed to a memory data interface for transferring data between a memory device and an integrated circuit, whereby, in accordance with one aspect of the present invention, the memory data interface includes a data selector for selecting and normalizing data from memory devices operating at different data transfer timing, and, in accordance with another aspect of the present invention, the memory data interface is capable of transferring data between a memory device and an integrated circuit having a different bus width than the memory device. In accordance with yet another aspect of the present invention, the memory data interface is capable of transferring data between an integrated circuit and a variety of different memory device having different data bus widths. Finally, in accordance with yet another aspect of the present invention, the memory data interface is capable of transferring data between an integrated circuit and a variety of memory devices having different bus widths and different data transfer timing.
摘要:
An address decoder selectively applies to word lines of a memory array individual signals of variable polarity, negative or positive, the value of which varies according to a word line address applied to the decoder. The decoder comprises a group decoder delivering signals for selecting a group of word lines of variable polarity, at least one subgroup decoder delivering signals for selecting a subgroup of word lines of variable polarity, and word line drivers each comprising means for multiplexing the group and subgroup selection signals, for selecting and selectively applying one of these signals to a word line. Advantages: reduction in the size of the terminating elements of the decoders in relation with the reduction of the technological pitch in Flash memories.