Invention Application
US20030133325A1 Architecture for a flash-EEPROM simultaneously readable in other sectors while erasing and/or programming one or more sectors
有权
在擦除和/或编程一个或多个扇区时，其他扇区可同时读取闪存EEPROM的架构
- Patent Title: Architecture for a flash-EEPROM simultaneously readable in other sectors while erasing and/or programming one or more sectors
- Patent Title (中): 在擦除和/或编程一个或多个扇区时，其他扇区可同时读取闪存EEPROM的架构
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Application No.: US10340207Application Date: 2003-01-10
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Publication No.: US20030133325A1Publication Date: 2003-07-17
- Inventor: Andrea Silvagni , Rino Micheloni , Giovanni Campardo
- Applicant: STMicroelectronics S.r.l.
- Applicant Address: IT Agrate Brianza
- Assignee: STMicroelectronics S.r.l.
- Current Assignee: STMicroelectronics S.r.l.
- Current Assignee Address: IT Agrate Brianza
- Priority: EP02425009.4 20020111
- Main IPC: G11C011/34
- IPC: G11C011/34
Abstract:
A memory device includes an array of memory cells organized into a plurality of sectors, and local wordlines and local bitlines are connected to the memory cells in each respective sector. Main read wordlines and main program wordlines are connected to the local wordlines in each sector. A main read row decoder is connected to the main read wordlines, and a main program row decoder connected to the main program wordlines. Main read bitlines and main program bitlines are connected to the local bitlines in each sector. A main read column decoder is connected to the main read bitlines, and a main program column decoder is connected to the main program wordlines. A read address bus is connected to the main read row decoder and to the main read column decoder for providing an address thereto. A program address bus is connected to the main read column decoder and to the main program row decoder for providing an address thereto.
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