公开(公告)号：US20030133325A1

公开(公告)日：2003-07-17

申请号：US10340207

申请日：2003-01-10

Applicant: STMicroelectronics S.r.l.

Inventor： Andrea Silvagni ,  Rino Micheloni ,  Giovanni Campardo

IPC: G11C011/34

CPC classification number: G11C16/08 ,  G11C2216/22

Abstract: A memory device includes an array of memory cells organized into a plurality of sectors, and local wordlines and local bitlines are connected to the memory cells in each respective sector. Main read wordlines and main program wordlines are connected to the local wordlines in each sector. A main read row decoder is connected to the main read wordlines, and a main program row decoder connected to the main program wordlines. Main read bitlines and main program bitlines are connected to the local bitlines in each sector. A main read column decoder is connected to the main read bitlines, and a main program column decoder is connected to the main program wordlines. A read address bus is connected to the main read row decoder and to the main read column decoder for providing an address thereto. A program address bus is connected to the main read column decoder and to the main program row decoder for providing an address thereto.

Abstract translation: 存储器件包括组织成多个扇区的存储器单元的阵列，并且本地字线和本地位线连接到每个相应扇区中的存储器单元。 主读取字线和主程序字线连接到每个扇区中的本地字线。 主读取行解码器连接到主读取字线，连接到主程序字线的主程序行解码器。 主读位线和主程序位线连接到每个扇区中的本地位线。 主读取列解码器连接到主读取位线，主程序列解码器连接到主程序字线。 读地址总线连接到主读行解码器和主读列解码器，以提供地址。 程序地址总线连接到主读取列解码器和主程序行解码器，以向其提供地址。