Invention Application
US20030134468A1 Aggressive capacitor array cell layout for narrow diameter DRAM trench capacitor structures via SOI technology
有权
用于通过SOI技术的窄直径DRAM沟槽电容器结构的积极电容器阵列单元布局
- Patent Title: Aggressive capacitor array cell layout for narrow diameter DRAM trench capacitor structures via SOI technology
- Patent Title (中): 用于通过SOI技术的窄直径DRAM沟槽电容器结构的积极电容器阵列单元布局
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Application No.: US10043477Application Date: 2002-01-11
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Publication No.: US20030134468A1Publication Date: 2003-07-17
- Inventor: Hsiao-Lei Wang , Chao-Hsi (Jesse) Chung , Hung-Kwei Liao
- Applicant: ProMOS Technologies, Inc.
- Applicant Address: null
- Assignee: ProMOS Technologies, Inc.
- Current Assignee: ProMOS Technologies, Inc.
- Current Assignee Address: null
- Main IPC: H01L021/8242
- IPC: H01L021/8242 ; H01L027/108

Abstract:
A method of increasing DRAM cell capacitance via formation of deep, wide diameter trench capacitor structures, has been developed. An underlying semiconductor substrate is used to accommodate deep, wide diameter trench capacitor structures while an overlying, bonded, thinned semiconductor substrate is used to accommodate narrow diameter trench structures, in turn used for communication to the underlying deep trench capacitor structures, as well as to accommodate the elements of the DRAM device, such as the transfer gate transistors. The use of an underlying semiconductor substrate for accommodation of the trench capacitor structures allows a wider diameter structures to be used, thus reducing patterning difficulties encountered when forming narrow diameter, deep trench capacitor structures.
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