公开(公告)号：US20040224503A1

公开(公告)日：2004-11-11

申请号：US10779634

申请日：2004-02-18

申请人： ProMos Technologies, Inc.

发明人： Cheng-ta Wu ,  Chang-Cheng Chen ,  Chun-Chi Chen

IPC分类号： H01L021/44

CPC分类号： B01D53/34 ,  B01D45/08 ,  B01D53/74 ,  B01J8/0065 ,  B01J12/00

摘要： A system for processing residual gas that includes a chamber having at least one baffle for increasing gas flow path, a residual gas inlet mechanism connected to the chamber for supplying residual gas to the chamber, at least one first gas inlet mechanism connected to the chamber for supplying inert gas to the chamber, at least one second gas inlet mechanism connected to the chamber for supplying a reactive gas to the chamber, and a gas outlet mechanism for connected to the chamber for outputting mixed gases from mixing the residual gas, inert gas and reactive gas and non-reacted residual gas, inert gas and reactive gas.

公开(公告)号：US20040178174A1

公开(公告)日：2004-09-16

申请号：US10600699

申请日：2003-06-23

申请人： ProMos Technologies, Inc.

发明人： Yung Hsien Wu

IPC分类号： C23F001/00

CPC分类号： H01L21/823462 ,  H01L21/28167 ,  H01L21/28202 ,  H01L21/3185 ,  H01L29/518

摘要： A method of manufacturing a semiconductor device includes providing a wafer substrate having a surface, forming a first nitride layer over the wafer substrate, providing a layer of photoresist over the first nitride layer, patterning and defining the photoresist layer, etching the first nitride layer unmasked by the photoresist to remove at least a portion of the first nitride layer to expose at least a portion of the substrate surface, removing the photoresist layer, and depositing a second nitride layer over the first nitride layer and the exposed substrate surface to form a nitride structure having a first thickness and a second thickness, wherein the first thickness includes a thickness of the first nitride layer.

摘要翻译： 制造半导体器件的方法包括提供具有表面的晶片衬底，在晶片衬底上形成第一氮化物层，在第一氮化物层上提供一层光致抗蚀剂，图案化和限定光致抗蚀剂层，蚀刻第一氮化物层未屏蔽 通过所述光致抗蚀剂去除所述第一氮化物层的至少一部分以暴露所述衬底表面的至少一部分，去除所述光致抗蚀剂层，以及在所述第一氮化物层和所述暴露的衬底表面上沉积第二氮化物层以形成氮化物 结构具有第一厚度和第二厚度，其中第一厚度包括第一氮化物层的厚度。

公开(公告)号：US20030143849A1

公开(公告)日：2003-07-31

申请号：US10393975

申请日：2003-03-24

申请人： ProMos Technologies Inc.

发明人： Ming-Cheng Yang ,  Jiun-Fang Wang

IPC分类号： H01L021/302 ,  H01L021/461

CPC分类号： H01L21/3212 ,  H01L21/76829 ,  H01L21/7684

摘要： A method for avoiding defects produced in The CMP process has the following steps: sequentially depositing a first dielectric layer and a second dielectric layer on a semiconductor substrate, wherein the wet-etching rate of the first dielectric layer is greater than the wet-etching rate of the second dielectric layer; forming a plurality of first holes on a plurality of the predetermined contact window areas respectively; wet etching the first dielectric layer in each of the first holes to form a plurality of second holes on the plurality of the predetermined contact window areas respectively; forming a conductive layer to fill each of the second holes; and performing the CMP process to level off the conductive layer and the second dielectric layer.

公开(公告)号：US20030102474A1

公开(公告)日：2003-06-05

申请号：US10004755

申请日：2001-12-03

申请人： ProMOS Technologies Inc.

发明人： Ting-Sing Wang

IPC分类号： H01L023/58

CPC分类号： H01L22/34

摘要： The present invention provides a semiconductor device for detecting gate defects and the method of using the same to detect gate defects. The semiconductor device is comprised of a semiconductor substrate having an oxide layer on the top, a gate having spacers, formed on the oxide layer and surrounding the semiconductor substrate, wherein the gate is also patterned to divide the semiconductor substrate into two parts not electrically connected, and a conductive layer formed on the semiconductor outside the gate. In addition, the method for using the semiconductor device of the present invention to detect gate defects is comprised of applying a ground voltage and a set voltage respectively to two parts divided by the gate in the semiconductor device, and measuring current between the two parts.

摘要翻译： 本发明提供一种用于检测栅极缺陷的半导体器件及其使用该方法来检测栅极缺陷。 半导体器件由在顶部具有氧化物层的半导体衬底，形成在氧化物层上并包围半导体衬底的间隔物的栅极组成，其中栅极也被图案化以将半导体衬底分成两个部分而不是电连接 以及形成在栅极外部的半导体上的导电层。 此外，使用本发明的半导体器件来检测栅极缺陷的方法包括分别将接地电压和设定电压施加到由半导体器件中的栅极划分的两个部分以及测量两个部分之间的电流。

公开(公告)号：US20030059996A1

公开(公告)日：2003-03-27

申请号：US10060590

申请日：2002-01-30

申请人： ProMos Technologies Inc.

发明人： Nien-Yu Tsai ,  Yung-Ching Wang

IPC分类号： H01L021/8238

CPC分类号： H01L21/76897 ,  H01L21/28247 ,  H01L21/823425 ,  H01L21/823475

摘要： A method for forming a gate structure is provided. The forming method includes steps of providing a semiconductor substrate; forming an insulation layer, a first gate conductor layer, a second gate conductor layer, and a masking layer on the semiconductor substrate; removing portions of the masking layer, the semiconductor substrate, and the first gate conductor layer to define the gate structure by etching; executing a cleaning process to the semiconductor with a specific cleaning agent for etching the second gate conductor layer, thereby removing portions of the second gate conductor layer in the gate structure; and performing a thermal treatment process to the semiconductor substrate and forming an insulation spacer on the side surface of the gate structure.

摘要翻译： 提供一种形成栅极结构的方法。 成形方法包括提供半导体衬底的步骤; 在半导体衬底上形成绝缘层，第一栅极导体层，第二栅极导体层和掩模层; 去除掩模层，半导体衬底和第一栅极导体层的部分，以通过蚀刻限定栅极结构; 利用用于蚀刻第二栅极导体层的特定清洁剂对半导体执行清洁处理，从而去除栅极结构中的第二栅极导体层的部分; 对所述半导体基板进行热处理，在所述栅极结构的侧面形成绝缘间隔物。

公开(公告)号：US20040209436A1

公开(公告)日：2004-10-21

申请号：US10681125

申请日：2003-10-09

申请人： ProMOS Technologies Inc.

发明人： Shih-Fang Chen

IPC分类号： H01L021/20

CPC分类号： H01L27/10861 ,  H01L27/10867

摘要： A trench capacitor process for preventing parasitic leakage. The process is capable of blocking leakage current from a parasitic transistor adjacent to the trench, and includes the steps of forming a doping layer and a cap layer covering portions of the sidewall of the trench and performing an annealing process on the doping layer to form a dopant region in the substrate adjacent to each sidewall of the trench and blocks leakage current from a parasitic transistor adjacent to the trench.

摘要翻译： 用于防止寄生泄漏的沟槽电容器工艺。 该过程能够阻挡来自与沟槽相邻的寄生晶体管的漏电流，并且包括以下步骤：形成掺杂层和覆盖沟槽的侧壁部分的覆盖层，并对掺杂层执行退火处理以形成 掺杂剂区域，并且阻挡来自与沟槽相邻的寄生晶体管的泄漏电流。

公开(公告)号：US20040115948A1

公开(公告)日：2004-06-17

申请号：US10317039

申请日：2002-12-12

申请人： ProMOS Technologies, Inc.

发明人： Yung Hsien Wu ,  Jer Lee

IPC分类号： H01L021/302

CPC分类号： H01L21/02238 ,  H01L21/022 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/3143

摘要： A method for manufacturing a semiconductor device that includes providing a first layer, cleaning the first layer, growing an oxide layer over the first layer at a reduced pressure from an atmospheric pressure, and depositing a nitride layer over the oxide layer, wherein the growing of the oxide layer and depositing of the nitride layer are performed in the same furnace.

摘要翻译： 一种制造半导体器件的方法，包括提供第一层，清洁第一层，在大气压力的减压下在第一层上生长氧化物层，以及在氧化物层上沉积氮化物层，其中生长 氧化物层和氮化物层的沉积在相同的炉中进行。

公开(公告)号：US20030139038A1

公开(公告)日：2003-07-24

申请号：US10138104

申请日：2002-05-03

申请人： ProMos Technologies, Inc.

发明人： S.C. Sun

IPC分类号： H01L021/4763 ,  H01L021/44

CPC分类号： H01L21/823842 ,  H01L21/823835

摘要： A method for manufacturing a semiconductor element is provided. The method includes a first silicon region, a second silicon region, and a metal silicide layer, wherein the metal silicide layer contacts with the first silicon region and the second silicon region separately, the method including steps of performing a first doping process to dope an N-type dopant into the first silicon region and to dope a diffusion barrier impurity into a portion of the metal silicide layer contacting with the first silicon region, and performing a second doping process to dope a P-type dopant into the second silicon region and to dope a diffusion barrier impurity into a portion of the metal silicide layer contacting with the second silicon region.

摘要翻译： 提供一种半导体元件的制造方法。 该方法包括第一硅区域，第二硅区域和金属硅化物层，其中金属硅化物层分别与第一硅区域和第二硅区域接触，该方法包括以下步骤：执行第一掺杂工艺以掺杂 将N型掺杂剂注入到第一硅区域中，并且将扩散阻挡杂质掺杂到与第一硅区接触的金属硅化物层的一部分中，以及执行第二掺杂工艺以将P型掺杂剂掺杂到第二硅区域中， 以将扩散阻挡杂质掺杂到与第二硅区接触的金属硅化物层的一部分中。

公开(公告)号：US20030127738A1

公开(公告)日：2003-07-10

申请号：US10305147

申请日：2002-11-27

申请人： ProMOS Technologies Inc.

发明人： Brian S. Lee ,  John Walsh

IPC分类号： H01L023/52 ,  H01L027/01 ,  H01L021/4763

CPC分类号： H01L21/28518 ,  H01L21/28525 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76859 ,  H01L21/823871

摘要： The present invention provides a semiconductor device in which a low resistance, tunable contact is formed by means of using a SixGe1nullx (0

摘要翻译： 本发明提供一种半导体器件，其中通过使用SixGe1-x（0

公开(公告)号：US20030049935A1

公开(公告)日：2003-03-13

申请号：US10218626

申请日：2002-08-15

申请人： PROMOS TECHNOLOGIES INC.

发明人： Hou-Hong Chou ,  Jiun-Fang Wang

IPC分类号： H01L021/302 ,  H01L021/461

CPC分类号： B08B1/04 ,  B08B3/08 ,  H01L21/02052 ,  H01L21/31053 ,  H01L21/31105

摘要： The present invention provides a method of removing residual particles from a polished surface. The method comprises the steps of: providing a substrate, forming a dielectric layer on the substrate, brush-cleaning and etching the dielectric layer on the substrate with a liquid when residual particles are lodged therein, whereby the residual particles are loosened and then relocated to the dielectric layer, and finally cleaning the dielectric layer to remove the relocated residual particles.

摘要翻译： 本发明提供从抛光表面除去残留颗粒的方法。 该方法包括以下步骤：提供衬底，在衬底上形成电介质层，当剩余颗粒沉积在其中时，用液体刷洗和蚀刻衬底上的电介质层，由此残留的颗粒松动然后重新定位到 介电层，最后清洁电介质层以除去重新定位的残留颗粒。