发明申请
US20030186502A1 STRUCTURE AND METHODS FOR PROCESS INTEGRATION IN VERTICAL DRAM CELL FABRICATION
有权
用于垂直DRAM单元制造过程集成的结构和方法
- 专利标题: STRUCTURE AND METHODS FOR PROCESS INTEGRATION IN VERTICAL DRAM CELL FABRICATION
- 专利标题(中): 用于垂直DRAM单元制造过程集成的结构和方法
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申请号: US10249997申请日: 2003-05-27
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公开(公告)号: US20030186502A1公开(公告)日: 2003-10-02
- 发明人: Rajeev Malik , Larry Nesbit , Jochen Beintner , Rama Divakaruni
- 申请人: INTERNATIONAL BUSINESS MACHINES CORPORATION , INFINEON TECHNOLOGIES NORTH AMERICA CORP.
- 申请人地址: US NY Armonk US CA San Jose
- 专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION,INFINEON TECHNOLOGIES NORTH AMERICA CORP.
- 当前专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION,INFINEON TECHNOLOGIES NORTH AMERICA CORP.
- 当前专利权人地址: US NY Armonk US CA San Jose
- 主分类号: H01L021/8242
- IPC分类号: H01L021/8242 ; H01L021/76
摘要:
A method for processing a semiconductor memory device is disclosed, the memory device including an array area and a support area thereon. In an exemplary embodiment of the invention, the method includes removing, from the array area, an initial pad nitride material formed on the device. The initial pad nitride material in the support area, however, is still maintained. Active device areas are then formed within the array area, wherein the initial pad nitride maintained in the support area helps to protect the support area from wet etch processes implemented during the formation of active device areas within the array area.
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