Invention Application
US20040023592A1 Field emission arrays and method of fabricating same to optimize the size of grid openings and to minimize the occurrence of electrical shorts 失效
场致发射阵列及其制造方法,以优化栅极开口的尺寸并最小化电短路的发生

  • Patent Title: Field emission arrays and method of fabricating same to optimize the size of grid openings and to minimize the occurrence of electrical shorts
  • Patent Title (中): 场致发射阵列及其制造方法,以优化栅极开口的尺寸并最小化电短路的发生
  • Application No.: US10615548
    Application Date: 2003-07-08
  • Publication No.: US20040023592A1
    Publication Date: 2004-02-05
  • Inventor: Ammar Derraa
  • Main IPC: H01J009/04
  • IPC: H01J009/04 H01J009/12
Field emission arrays and method of fabricating same to optimize the size of grid openings and to minimize the occurrence of electrical shorts
Abstract:
A method for fabricating a field emission structure is disclosed. A first dielectric layer and a second material layer are disposed over a substrate and at least one emitter tip thereon. Planarization of the second layer exposes regions of the first layer that cover the emitter tip, which regions may then be removed through the second layer. Substantially Substantial removal of the second layer reduces any conductive defects that protrude from a surface of the first layer. A third, dielectric layer and fourth, grid layer are then formed. Planarization of the fourth layer forms grid openings and exposes dielectric material of the third layer which overlies the emitter tip. Dielectric material of one or both underlying layers may then be removed to expose the outer surfaces of the emitter tip.
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