发明申请
- 专利标题: Anti-deadlock circuit and method for phase-locked loops
- 专利标题(中): 防死锁电路和锁相环的方法
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申请号: US10330559申请日: 2002-12-30
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公开(公告)号: US20040124936A1公开(公告)日: 2004-07-01
- 发明人: Shenggao Li
- 主分类号: H03B005/32
- IPC分类号: H03B005/32
摘要:
A system and method for controlling a phase-locked loop detects a deadlock condition and then adjusts an output frequency of an oscillator until the deadlock condition is corrected. The deadlock condition may be detected based on a value of a charge pump signal which controls the oscillator frequency. In accordance with one embodiment, deadlock is detected if the value of the charge pump signal approaches one of two supply rail voltages. The deadlock condition is overcome by manipulating current signals output from the charge pump. This is accomplished by turning off the current from one charge-pump current source and increasing current from a second-charge pump current source. The increased current may be provided by a third current source located within or external to the charge pump. By adding current from the third current source, the output frequency of the phase-locked loop will be driven lower until a value is reached which effectively pulls the PLL out of the deadlock condition.
公开/授权文献
- US06853254B2 Anti-deadlock circuit and method for phase-locked loops 公开/授权日:2005-02-08
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