A method and apparatus for reducing pin overhead in a non-scan design for testability is disclosed. In one embodiment, the method comprises: connecting control signals of test points l1, l2, . . . , lh to a first primary input PI1 through AND gate switch, connecting control signals of test points lj, . . . , lq to a second primary input PI2 through AND gate switch until every test point is connected to either primary inputs PI1 or PI2, connecting a 1-control point to AND gate directly, connecting a 0-control point to AND gate through inverter, sharing one AND gate among all control points that are connected to the same primary input, controlling all control points by an uniform signal test, and checking whether the test points and the primary inputs produce new re-convergent fan-out while reducing inputs of the control signals. In another embodiment, the apparatus comprises: means for connecting control signals of test points l1, l2, . . . , lh to a first primary input PI1 through AND gate switch, means for connecting control signals of test points lj, . . . , lq to a second primary input PI2 through AND gate switch until every test point is connected to either primary inputs PI1 or PI2, means for connecting a 1-control point to AND gate directly, means for connecting a 0-control point to AND gate through inverter, means for sharing one AND gate among all control points that are connected to the same primary input, means for controlling all control points by an uniform signal test, and means for checking whether the test points and the primary inputs produce new re-convergent fan-out while reducing inputs of the control signals.