公开(公告)号：US20040257066A1

公开(公告)日：2004-12-23

申请号：US10726891

申请日：2003-12-04

申请人： Matsushita Elec. Ind. Co. Ltd.

发明人： Satoru Kamano ,  Tomohiko Kanemitsu

IPC分类号： G01R001/00

CPC分类号： G01R31/31907

摘要： An ancillary equipment is provided for testing a semiconductor integrated circuit, by which a plurality of BOST boards serving as measuring units can be set near a device to be measured and tests can be conducted with high accuracy on a number of circuits embedded on a semiconductor integrated circuit such as a system LSI. To achieve an object of performing a go/no go test or a functional/performance characterization in the manufacturing process of the semiconductor integrated circuit, the ancillary equipment includes: a device measuring unit having a measuring section for exchanging a signal with a device or a semiconductor integrated circuit, and an analyzing section for analyzing information from the measuring section using a programmable device; and a control/communication card constituted of a board different from that of the device measuring unit and connected to the device measuring unit to control it, and being capable of performing communication with a general-purpose computer.

摘要翻译： 提供了用于测试半导体集成电路的辅助设备，通过该半导体集成电路可以将多个用作测量单元的BOST板设置在要测量的设备附近，并且可以在嵌入在半导体集成电路上的多个电路上以高精度进行测试 电路如系统LSI。 为了实现在半导体集成电路的制造过程中执行去/禁止测试或功能/性能表征的目的，辅助设备包括：设备测量单元，具有用于与设备或设备交换信号的测量部分 半导体集成电路和用于使用可编程器件分析来自测量部分的信息的分析部分; 以及由与设备测量单元不同的板构成的控制/通信卡，并连接到设备测量单元以进行控制，并且能够与通用计算机进行通信。

公开(公告)号：US20040245981A1

公开(公告)日：2004-12-09

申请号：US10453612

申请日：2003-06-04

发明人： Andrew H. Barr ,  Ken G. Pomaranski ,  Dale J. Shidla

IPC分类号： G01R001/00

CPC分类号： G01R31/2884 ,  G01R31/046

摘要： A method and corresponding apparatus for detecting and rejecting high impedance failures in chip interconnects use monitoring circuitry on a chip to provide accurate and pro-active prediction of interconnect failures. The apparatus may include a resistance continuity monitoring circuit (RCMC), and a signal path connecting a representative set of pins to the RCMC. The RCMC measures the resistance of a connection of the representative set of pins with a circuit board during system operation and outputs a measured resistance data. The apparatus further includes additional analog-to-digital (A/D) hardware to perform an analog to digital conversion of the measured resistance data. Additional on-chip circuitry and/or microcode may be used to perform an algorithm on the digital resistance data to generate an interconnect status signal. For example, the method may output a failure signal when the measured resistance data exceeds a threshold resistance value. The apparatus further includes a system interface to send the interconnect status signal to other system management devices.

摘要翻译： 用于检测和拒绝芯片互连中的高阻抗故障的方法和相应的装置使用芯片上的监视电路来提供对互连故障的准确和主动的预测。 该装置可以包括电阻连续性监视电路（RCMC），以及将代表性的一组引脚连接到RCMC的信号路径。 RCMC在系统运行期间测量代表性的一组引脚与电路板的连接电阻，并输出测量的电阻数据。 该装置还包括附加的模数（A / D）硬件，以对所测量的电阻数据进行模数转换。 可以使用附加的片上电路和/或微代码来对数字电阻数据执行算法以产生互连状态信号。 例如，当测量的电阻数据超过阈值电阻值时，该方法可以输出故障信号。 该装置还包括将互连状态信号发送到其他系统管理装置的系统接口。

公开(公告)号：US20040244192A1

公开(公告)日：2004-12-09

申请号：US10454649

申请日：2003-06-03

发明人： Chung Hsien Hsin ,  Hsiu-Wen Tu ,  Jason Chuang ,  Irving You

IPC分类号： H05K003/30 ,  G01R001/00

CPC分类号： H01L27/14685 ,  H01L27/14618 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/16195 ,  Y10T29/49004 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49144 ,  Y10T29/49169 ,  H01L2924/00014

摘要： A method for packaging an image sensor includes the steps of: providing a substrate having an upper surface and a lower surface; mounting a frame layer to the upper surface of the substrate to form a chamber together with the substrate; mounting a photosensitive chip to the upper surface of the substrate and within the chamber, and electrically connecting the photosensitive chip to the substrate; mounting a transparent layer to the frame layer with a B-stage adhesive applied therebetween; pre-baking the B-stage adhesive to slightly adhere the transparent layer to the frame layer; testing the image sensor to determine whether the image sensor is passed or failed; and post-baking the passed image sensor to completely cure the B-stage adhesive so that the transparent layer is firmly adhered to the frame layer.

摘要翻译： 包装图像传感器的方法包括以下步骤：提供具有上表面和下表面的基底; 将框架层安装到基板的上表面以与基板一起形成室; 将光敏芯片安装到基板的上表面和室内，并将感光芯片电连接到基板上; 在其间施加B阶粘合剂将透明层安装到框架层; 预烘烤B阶粘合剂以将透明层稍微粘附到框架层; 测试图像传感器以确定图像传感器是否通过或失败; 并且对通过的图像传感器进行后烘烤以完全固化B级粘合剂，使得透明层牢固地粘附到框架层。

公开(公告)号：US20040239310A1

公开(公告)日：2004-12-02

申请号：US10889379

申请日：2004-07-12

发明人： Hideyuki Oshima ,  Yasutaka Tsuruki

IPC分类号： G01R001/00

CPC分类号： G01R31/31922 ,  G01R31/31928

摘要： A tester comprising a reference clock generating section for generating a reference clock having a first frequency, a first test rate generating section for generating a first test rate clock having a frequency which is about an integral multiple of the first frequency, a second test rate generating section for generating a second test rate clock having a frequency which is about an integral multiple of the first frequency and different from the frequency of the first test rate clock, a first driver section for supplying a test pattern to an electronic device according to the first test rate clock, and a second deriver section for supplying the test pattern to the electronic device according to the second test rate clock.

摘要翻译： 一种测试器，包括用于产生具有第一频率的参考时钟的参考时钟产生部分，用于产生具有大约是第一频率的整数倍的频率的第一测试速率时钟的第一测试速率产生部分，产生第二频率的第二测试速率 用于产生具有大约是第一频率的整数倍并且不同于第一测试速率时钟的频率的频率的第二测试速率时钟的第一测试速率时钟;第一驱动器部分，用于将测试图案提供给根据第一测试时钟的电子设备 测试速率时钟，以及第二提升部分，用于根据第二测试速率时钟将测试图案提供给电子设备。

公开(公告)号：US20040237285A1

公开(公告)日：2004-12-02

申请号：US10492612

申请日：2004-04-15

发明人： Pelle Rangsten ,  Edvard Kalvesten ,  Marianne Mechbach

IPC分类号： H01S004/00 ,  G01R001/00

CPC分类号： G01L9/0042 ,  G01L9/0055 ,  Y10T29/49002 ,  Y10T29/49004 ,  Y10T29/49007

摘要： In manufacturing a pressure sensor a recess that will form part of the sensor cavity is formed in a lower silicon substrate. An SOI-wafer having a monocrystalline silicon layer on top of a substrate is bonded to the lower silicon substrate closing the recess and forming the cavity. The supporting substrate of the SOI-wafer is then etched away, the portion of the monocrystalline layer located above the recess forming the sensor diaphragm. The oxide layer of the SOI-wafer here acts as an nullidealnull etch stop in the case where the substrate wafer is removed by dry (plasma) or wet etching using e.g. KOH. This is due to high etch selectivity between silicon and oxide for some etch processes and it results in a diaphragm having a very accurately defined and uniform thickness. The cavity is evacuated by forming a opening to the cavity and then sealing the cavity by closing the opening using LPCVD. Sensor paths for sensing the deflection of the diaphragm are applied on the outer or inner surface of the diaphragm. The monocrystalline diphragm gives the sensor a good long-term stability. Also the sensor path can be made of monocrystalline material, this giving the sensor even better good long-term characteristics. An increased sensitivity can be obtained by making active portions of the sensor paths freely extending, unsupported by other material of the pressure sensor, by suitable etching procedures.

摘要翻译： 在制造压力传感器中，形成传感器腔的一部分的凹部形成在下硅衬底中。 在衬底顶部具有单晶硅层的SOI晶片被接合到下硅衬底上，封闭凹部并形成空腔。 然后蚀刻掉SOI晶片的支撑衬底，单晶层的部分位于形成传感器膜片的凹部之上。 SOI晶片的氧化物层在此通过干式（等离子体）或湿式蚀刻方式除去基板晶片的情况下，作为“理想的”蚀刻停止。 KOH。 这是由于在一些蚀刻工艺之间硅和氧化物之间的高蚀刻选择性，并且其导致膜具有非常精确地限定和均匀的厚度。 通过向腔体形成开口并且然后通过使用LPCVD闭合开口来密封空腔来抽空空腔。 用于感测隔膜偏转的传感器路径被施加在隔膜的外表面或内表面上。 单晶diphragm给传感器良好的长期稳定性。 此外，传感器路径也可以由单晶材料制成，这给传感器带来更好的长期特性。 传感器路径的有效部分通过适当的蚀刻程序自由延伸，不受压力传感器的其他材料支撑，可以获得增加的灵敏度。

公开(公告)号：US20040227504A1

公开(公告)日：2004-11-18

申请号：US10788670

申请日：2004-02-27

申请人： Applied Precision, LLC

发明人： John T. Strom

IPC分类号： G01R001/00

CPC分类号： G01R31/2891 ,  G01R1/06794 ,  G01R1/07342 ,  G01R31/2886 ,  G01R35/00

摘要： By examining scrub mark properties (such as position and size) directly, the performance of a wafer probing process may be evaluated. Scrub mark images are captured, image data measured, and detailed information about the process is extracted through analysis. The information may then be used to troubleshoot, improve, and monitor the probing process.

摘要翻译： 通过直接检查洗刷标记特性（如位置和尺寸），可以评估晶圆探测过程的性能。 通过分析提取清洗标记图像，测量图像数据，并提取有关过程的详细信息。 然后可以使用该信息来排除故障，改进和监控探测过程。

公开(公告)号：US20040174308A1

公开(公告)日：2004-09-09

申请号：US10382406

申请日：2003-03-04

发明人： Chung Shu Chang

IPC分类号： G01R001/00

CPC分类号： G01R29/0878 ,  G01R19/155

摘要： An electricity detecting and testing device includes a detecting device having an antenna to detect signals of either an electric field or an electromagnetic field, signal generating device for generating indicating signals, two conductors, one or more batteries, and a switch coupled to the batteries, to selectively couple the batteries to either the detecting device or the conductors. The conductors may be used to test whether the electric members have been damaged or not. The detecting device may be used to detect whether an electric current or energy has been supplied through the detected electric facilities or not.

摘要翻译： 电检测装置包括具有检测电场或电磁场的信号的天线的检测装置，用于产生指示信号的信号发生装置，两个导体，一个或多个电池以及耦合到电池的开关， 选择性地将电池耦合到检测装置或导体。 导体可用于测试电气部件是否已损坏。 检测装置可以用于检测是否通过检测到的电气设备提供电流或能量。

公开(公告)号：US20040155824A1

公开(公告)日：2004-08-12

申请号：US10760949

申请日：2004-01-20

发明人： Masami Nagashima

IPC分类号： G01R001/00

CPC分类号： G01R29/10

摘要： According to the present invention, a small-sized electromagnetic wave measuring apparatus is provided which can simply measure an electromagnetic wave radiated from an antenna to be measured. The electromagnetic wave includes: a holder for holding the antenna to be measured; a plurality of probe antennas, provided on a circle having a center substantially at the holder, for detecting the electromagnetic wave radiated from the antenna to be measured; and a rotating unit for rotating the holder around a direction substantially perpendicular to a normal of the circle as a rotation axis.

摘要翻译： 根据本发明，提供一种小型电磁波测量装置，其可以简单地测量从待测天线辐射的电磁波。 电磁波包括：用于保持待测天线的支架; 多个探针天线，设置在具有大致位于所述保持器的中心的圆上，用于检测从待测天线辐射的电磁波; 以及旋转单元，用于使保持器围绕基本上垂直于圆的法线的方向作为旋转轴旋转。

公开(公告)号：US20040154161A1

公开(公告)日：2004-08-12

申请号：US10677180

申请日：2003-10-02

申请人： Hallys Corporation

发明人： Hiroshi Aoyama ,  Ryoichi Nishigawa

IPC分类号： B23P019/00 ,  G01R001/00

CPC分类号： B65G47/848 ,  B65G29/00 ,  G06K19/07718 ,  G06K19/07749 ,  G06K19/0775 ,  H01L21/67132 ,  H01L21/67144 ,  H05K13/02 ,  Y10T29/49004 ,  Y10T29/4913 ,  Y10T29/53039 ,  Y10T29/5313 ,  Y10T29/53174 ,  Y10T29/53178 ,  Y10T29/53191

摘要： A chip transfer apparatus includes a first carrier for feeding chips and a second carrier for carrying works on it. The transfer apparatus also includes a transfer engine including two or more coaxial revolvers, which can revolve coaxially with each other. Each of the coaxial revolvers includes an end-effector for receiving a chip from the first carrier and transferring the received chip onto a work on the second carrier. The end-effectors of the coaxial revolvers are arranged in a circle coaxial with the revolvers. The end-effectors sequentially receive chips from the first carrier at substantially zero speed relative to the first carrier and transfer the received chips onto works on the second carrier at substantially zero speed relative to the second carrier. While the end-effectors are revolving, they undergo periodic speed change control for timing adjustment and speed adjustment for the chip reception and transfer.

摘要翻译： 芯片传送装置包括用于馈送芯片的第一载体和用于在其上承载作品的第二载体。 传送装置还包括一个传送引擎，该传送引擎包括两个或更多个可同轴旋转的同轴旋转轮。 每个同轴旋转器包括用于从第一载体接收芯片并将接收的芯片传送到第二载体上的工件的端部执行器。 同轴罗拉的末端执行器布置成与左轮手枪同轴的圆周。 端部执行器相对于第一载体以基本上零速的顺序地从第一载体接收芯片，并将接收到的芯片以相对于第二载体的基本零速度传送到第二载体上的工件。 当端部执行器旋转时，它们进行周期性的速度变化控制，用于芯片接收和传输的定时调整和速度调节。

公开(公告)号：US20040130313A1

公开(公告)日：2004-07-08

申请号：US10703936

申请日：2003-11-07

发明人： Dong Xiang ,  Jiaguang Sun

IPC分类号： G01R001/00

CPC分类号： G01R31/31723 ,  G01R31/31704

摘要： A method and apparatus for reducing pin overhead in a non-scan design for testability is disclosed. In one embodiment, the method comprises: connecting control signals of test points l1, l2, . . . , lh to a first primary input PI1 through AND gate switch, connecting control signals of test points lj, . . . , lq to a second primary input PI2 through AND gate switch until every test point is connected to either primary inputs PI1 or PI2, connecting a 1-control point to AND gate directly, connecting a 0-control point to AND gate through inverter, sharing one AND gate among all control points that are connected to the same primary input, controlling all control points by an uniform signal test, and checking whether the test points and the primary inputs produce new re-convergent fan-out while reducing inputs of the control signals. In another embodiment, the apparatus comprises: means for connecting control signals of test points l1, l2, . . . , lh to a first primary input PI1 through AND gate switch, means for connecting control signals of test points lj, . . . , lq to a second primary input PI2 through AND gate switch until every test point is connected to either primary inputs PI1 or PI2, means for connecting a 1-control point to AND gate directly, means for connecting a 0-control point to AND gate through inverter, means for sharing one AND gate among all control points that are connected to the same primary input, means for controlling all control points by an uniform signal test, and means for checking whether the test points and the primary inputs produce new re-convergent fan-out while reducing inputs of the control signals.

摘要翻译： 公开了一种用于在非扫描设计中减少引脚开销的可测试性的方法和装置。 在一个实施例中，该方法包括：连接测试点11,112的控制信号。 。 。 ，lh到第一个主输入PI1到AND门开关，连接测试点lj的控制信号。 。 。 ，lq到第二个主输入端PI2到AND门开关，直到每个测试点连接到主输入PI1或PI2，将一个控制点直接连接到与门，将0控制点连接到与门通过逆变器共享 连接到同一主输入的所有控制点中的一个与门，通过统一信号测试控制所有控制点，并检查测试点和主输入是否产生新的再收敛扇出，同时减少控制的输入 信号。 在另一个实施例中，该装置包括：用于连接测试点11,112的控制信号的装置。 。 。 对于第一主输入端PI1至AND门开关，用于连接测试点lj的控制信号的装置。 。 。 通过AND门开关将Iq连接到第二主输入端PI2，直到每个测试点连接到主输入端PI1或PI2为止，用于将1控制点直接连接到与门的装置，用于将0控制点连接到与门 通过逆变器，用于在连接到相同主输入的所有控制点之间共享一个与门的装置，用于通过统一的信号测试来控制所有控制点的装置，以及用于检查测试点和主要输入是否产生新的重新连接的装置， 收敛扇出，同时减少控制信号的输入。