A clock signal driven device has a clock pin for receiving an externally generated clock signal during normal operation. Internal circuitry coupled to the clock pin is responsive to the externally generated clock signal during normal operation. The device also has a clock source, such as a PLL, that provides an internal clock signal, and an internal clock generator that during a test mode of operation generates from the internal clock signal and asserts on the clock pin a test clock signal. The test clock signal has substantially similar signal characteristics to predefined signal characteristics of the externally generated clock signal. The device's internal circuitry is responsive to the test clock signal during the test mode of operation.