公开(公告)号：US20040260962A1

公开(公告)日：2004-12-23

申请号：US10601441

申请日：2003-06-23

发明人： Victor Suen ,  William Lau ,  Hui-Yin Seto

IPC分类号： G06F001/12

CPC分类号： H03K5/135 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096

摘要： Systems and methods are provided for latching a data signal. In one embodiment, a system comprises a first delay circuit that programmably delays a strobe signal with a first delay to latch a data signal. The system also comprises a second delay circuit that receives the data signal and delays the data signal with a second delay that is substantially inherent to the first delay. The system may include a logic circuit coupled between the first and the second delay circuits for latching the data signal in substantial alignment with the strobe signal. In one embodiment, similar delays are used in a master delay circuit, while in another embodiment such delays are used in slave devices connected to a master delay circuit.

摘要翻译： 提供了用于锁存数据信号的系统和方法。 在一个实施例中，系统包括第一延迟电路，其可编程地延迟具有第一延迟的选通信号以锁存数据信号。 系统还包括第二延迟电路，其接收数据信号并以第一延迟基本固有的第二延迟来延迟数据信号。 该系统可以包括耦合在第一和第二延迟电路之间的逻辑电路，用于锁存与选通信号基本对准的数据信号。 在一个实施例中，在主延迟电路中使用相似的延迟，而在另一实施例中，这种延迟用于连接到主延迟电路的从设备。

公开(公告)号：US20040250151A1

公开(公告)日：2004-12-09

申请号：US10483511

申请日：2004-07-09

发明人： Torsten Abendroth ,  Maren Abendroth ,  Hans-Ulrich Fleer

IPC分类号： G06F001/12

CPC分类号： H04L7/0012 ,  G05B19/0428 ,  G05B19/4063 ,  G05B2219/24026 ,  G05B2219/24056 ,  G05B2219/25039 ,  G05B2219/25258

摘要： A status indication detection apparatus (SIDM) comprises an input storage stage (INS), an intermediate storage stage (ISS) and an output storage stage (OSS). Status indications (IN STATUS) are input into the input register (INM) of the input stage (INS) and are shifted to the intermediate and to the output stage (ISS; OSS). The input and intermediate storage stages operate with a first reference clock (CLK-A) in a first clock domain (A) whilst the output storage stage operates with a different second reference clock (CLK-B) in the second clock domain (B). In accordance with the invention a reading out of the intermediate register (INT) of the intermediate stage (ISS) is only possible during the generation of a hold signal (LOCK) which keeps a current status indication in the intermediate storage stage (ISS) and blocks a transfer of a new status indication from the input stage (INS). Since the hold signal (LOCK) duration covers at lest one second clock reference period, a read out pulse (STROBE) can be placed within the hold signal duration (LOCKL). Thus, even at different phase and/or frequency relationships between the first and second reference clock (CLK-A, CLK-B) a metastability in the output register (ORM) can be avoided and no status indications output from the hardware device (HW) get lost.

摘要翻译： 状态指示检测装置（SIDM）包括输入存储级（INS），中间存储级（ISS）和输出存储级（OSS）。 状态指示（IN STATUS）被输入到输入级（INS）的输入寄存器（INM）中，并被移入中间级和输出级（ISS; OSS）。 输入和中间存储级在第一时钟域（A）中以第一参考时钟（CLK-A）操作，而输出存储级在第二时钟域（B）中以不同的第二参考时钟（CLK-B）操作， 。 根据本发明，中间级（ISS）的中间寄存器（INT）的读出仅在生成保持中间存储级（ISS）中的当前状态指示的保持信号（LOCK）和 阻止来自输入级（INS）的新状态指示的传送。 由于保持信号（LOCK）持续时间至少覆盖一个第二时钟参考周期，读出脉冲（STROBE）可以被置于保持信号持续时间（LOCKL）内。 因此，即使在第一和第二参考时钟（CLK-A，CLK-B）之间的不同相位和/或频率关系下，也可以避免输出寄存器（ORM）中的亚稳态，并且不会从硬件设备（HW ） 走开。

公开(公告)号：US20040243870A1

公开(公告)日：2004-12-02

申请号：US10830341

申请日：2004-04-22

申请人： AGILENT TECHNOLOGIES, INC.

发明人： Thomas Henkel ,  Ralf Killig

IPC分类号： G06F001/12

CPC分类号： G01R31/31922 ,  G06F1/10

摘要： A multi-channel architecture comprising a central facility that is under clock control of a central facility's clock signal, and a central transfer clock generator adapted for deriving a central transfer clock signal from the central facility's clock signal. The multi-channel architecture further comprises a set of n channels, with n being a natural number, wherein each channel is under clock control of one out of a plurality of clock signals. Each of the channels comprises a channel transfer clock generator adapted for deriving a channel transfer clock signal from a clock signal of the respective channel, wherein the central facility's clock signal and the clock signals of the channels comprise at least two different clock signals. The transfer clock period of the central transfer clock signal is substantially equal to each of the transfer clock periods of the channel transfer clock signals.

摘要翻译： 一种多通道架构，包括中央设备的时钟信号的时钟控制的中央设备和适于从中央设施的时钟信号导出中央传送时钟信号的中央传送时钟发生器。 多通道架构还包括一组n个通道，其中n是自然数，其中每个通道处于多个时钟信号中的一个的时钟控制之下。 每个信道包括适于从相应信道的时钟信号导出信道传输时钟信号的信道传输时钟发生器，其中中心设备的时钟信号和信道的时钟信号包括至少两个不同的时钟信号。 中央传送时钟信号的传送时钟周期基本上等于信道传输时钟信号的每个传送时钟周期。

公开(公告)号：US20040243869A1

公开(公告)日：2004-12-02

申请号：US10452247

申请日：2003-05-30

申请人： Sun Microsystems, Inc.

发明人： Anup K. Sharma ,  Venkatram Krishnaswamy

IPC分类号： G06F001/12

CPC分类号： G06F1/12

摘要： A method for communicating across first and second frequency domains of an integrated microchip is provided. The method initiates with determining a clock ratio between the first frequency domain and the second frequency domain. The first frequency domain is associated with a faster clock cycle. Then, a synchronizing signal based upon the clock ratio is generated. The synchronizing signal coordinates communication of data between the first and second frequency domains. Next, the data is transferred between respective frequency domains according to the synchronizing signal. A microchip and a system enabling synchronous data transfer across different frequency domains are also provided.

摘要翻译： 提供了一种用于在集成微芯片的第一和第二频域上通信的方法。 该方法通过确定第一频域和第二频域之间的时钟比来启动。 第一个频域与更快的时钟周期相关联。 然后，产生基于时钟比的同步信号。 同步信号协调第一和第二频域之间的数据通信。 接下来，根据同步信号在各个频域之间传送数据。 还提供了一种微芯片和实现跨不同频域的同步数据传输的系统。

公开(公告)号：US20040236979A1

公开(公告)日：2004-11-25

申请号：US10794233

申请日：2004-03-05

发明人： Jeffrey R. Wilcox ,  Gad S. Sheaffer

IPC分类号： G06F001/12

CPC分类号： G06F5/06 ,  G06F1/12

摘要： A method and apparatus for a integrated circuit having flexible-ratio frequency domain cross-overs. In one embodiment, an integrated circuit has at least three cooperating frequency domains with variable operating frequencies. The integrated circuit includes cross-over logic to allow integral fraction ratio frequency domain cross-overs between more than one pair of frequency domains.

摘要翻译： 一种具有灵活比率频域交叉的集成电路的方法和装置。 在一个实施例中，集成电路具有至少三个具有可变工作频率的协作频域。 集成电路包括交叉逻辑，以允许多于一对频域之间的积分分数比频域交叉。

公开(公告)号：US20040236976A1

公开(公告)日：2004-11-25

申请号：US10441856

申请日：2003-05-20

发明人： Charles Johnson

IPC分类号： G06F001/12

CPC分类号： H03K5/135 ,  G04G3/00 ,  H03K2005/0011

摘要： As provided, a system and method for automatically correcting timers to improve timing accuracy. The system and method provides for the use of inexpensive low tolerance resonators or oscillators that meet the internal timing specifications of applications of isochronous I/O over Profibus. Accordingly, the specified error rate (jitter) to appropriately maintain I/O is met efficiently and at low cost.

摘要翻译： 提供一种用于自动校正定时器以提高定时精度的系统和方法。 该系统和方法提供了使用符合Profibus同步I / O应用的内部时序规范的便宜的低容差谐振器​​或振荡器。 因此，以有效且低成本地满足适当地保持I / O的规定的错误率（抖动）。

公开(公告)号：US20040230854A1

公开(公告)日：2004-11-18

申请号：US10435970

申请日：2003-05-12

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： David A. Elko ,  Richard K. Errickson ,  Steven N. Goss ,  Dan F. Greiner ,  Carol B. Hernandez ,  Ronald M. Smith SR. ,  David H. Surman

IPC分类号： G06F001/12

CPC分类号： G06F9/546

摘要： A method for providing a message-time-ordering facility is disclosed. The method comprises initiating the message-timer ordering facility for a message at a sender system. Initiating includes setting a delay variable to zero. The message is sent to a receiver system in response to initiating the message-time-ordering facility. Sending the message includes marking the message with a first departure time-stamp responsive to a sender system clock and transmitting the message to the receiver system. The message is received at the at the receiver system, receiving includes delaying the processing of the message until the time on a receiver system clock is greater than the first departure time-stamp and recording a time associated with the delaying the processing of the message in the delay variable. A response to the message is sent to the sender system in response to receiving the message. Sending the response includes marking the response with a second departure time-stamp responsive to the receiver system clock if the delay variable is equal to zero and transmitting the response to the sender system. The response is received at the sender system. Receiving the response includes delaying the processing of the response if the delay variable is equal to zero until the time on the sender system clock is greater than the second departure time-stamp and recording a time associated with the delaying the processing of the response in the delay variable.

摘要翻译： 公开了一种提供消息时间排序设施的方法。 该方法包括在发送者系统处发起消息的消息定时器排序设施。 启动包括将延迟变量设置为零。 响应于启动消息时间排序设施，该消息被发送到接收机系统。 发送消息包括响应于发送者系统时钟的第一起始时间戳来标记消息并将消息发送到接收机系统。 消息在接收机系统处被接收，接收包括延迟消息的处理，直到接收机系统时钟的时间大于第一个出发时间戳，并且记录与将消息的处理延迟相关联的时间 延迟变量。 响应于接收到该消息，对该消息的响应被发送到发送者系统。 发送响应包括响应于接收机系统时钟的第二个出发时间戳来标记响应，如果延迟变量等于零并将响应发送到发送器系统。 发送方系统收到响应。 如果延迟变量等于0，则接收响应包括延迟响应的处理，直到发送方系统时钟的时间大于第二个出发时间戳，并记录与延迟处理响应相关的时间 延迟变量。

公开(公告)号：US20040221188A1

公开(公告)日：2004-11-04

申请号：US10857707

申请日：2004-05-27

申请人： Rambus Inc.

发明人： Benedict C. Lau ,  Leung Yu

IPC分类号： G06F001/12

CPC分类号： G11C29/12015 ,  G11C29/14

摘要： A clock signal driven device has a clock pin for receiving an externally generated clock signal during normal operation. Internal circuitry coupled to the clock pin is responsive to the externally generated clock signal during normal operation. The device also has a clock source, such as a PLL, that provides an internal clock signal, and an internal clock generator that during a test mode of operation generates from the internal clock signal and asserts on the clock pin a test clock signal. The test clock signal has substantially similar signal characteristics to predefined signal characteristics of the externally generated clock signal. The device's internal circuitry is responsive to the test clock signal during the test mode of operation.

摘要翻译： 时钟信号驱动器件具有用于在正常操作期间接收外部产生的时钟信号的时钟引脚。 耦合到时钟引脚的内部电路在正常操作期间响应于外部产生的时钟信号。 该器件还具有提供内部时钟信号的时钟源，例如PLL，以及内部时钟发生器，在测试操作模式期间，从内部时钟信号产生，并在时钟引脚上产生测试时钟信号。 测试时钟信号具有与外部产生的时钟信号的预定信号特性基本相似的信号特性。 在测试操作模式下，器件的内部电路响应测试时钟信号。

公开(公告)号：US20040133820A1

公开(公告)日：2004-07-08

申请号：US10663977

申请日：2003-09-17

申请人： Oki Electric Industry Co., Ltd.

发明人： Hirohisa Tanabe ,  George Fukutomi ,  Shinji Hiratsuka ,  Hirofumi Odaguchi

IPC分类号： G06F001/04 ,  G06F001/12 ,  G06F005/06

CPC分类号： G06F5/06 ,  G06F1/04 ,  G06F1/12

摘要： Noise removal and detection are performed for a signal VBUS in a detection portion in accordance with a low-frequency clock signal CLK generated by a CR oscillation circuit, and a detection signal VBD is received by a process control portion. A signal VBC detected by the detection portion is supplied to a quartz oscillation circuit as an operation-enable signal ENB. Thus, when a data transmission is designated by the signal VBUS, the quartz oscillation circuit supplies a high-frequency clock signal CK to a transmission function portion, enabling a data transmission. The operation-enable signal ENB is not supplied to the quartz oscillation circuit when data transmission is not performed. The power consumption of the CR oscillation circuit is small, so power consumption can be reduced.

摘要翻译： 根据由CR振荡电路产生的低频时钟信号CLK，对检测部分中的信号VBUS执行噪声去除和检测，并且检测信号VBD由处理控制部分接收。 由检测部分检测的信号VBC被提供给石英振荡电路作为操作使能信号ENB。 因此，当由信号VBUS指定数据传输时，石英振荡电路将高频时钟信号CK提供给发送功能部分，从而实现数据传输。 当不执行数据传输时，操作使能信号ENB不提供给石英振荡电路。 CR振荡电路的功耗很小，因此可以降低功耗。

公开(公告)号：US20040103336A1

公开(公告)日：2004-05-27

申请号：US10302236

申请日：2002-11-22

发明人： Jose L. Flores ,  Lewis Nardini

IPC分类号： G06F001/12

CPC分类号： G06F9/3869 ,  G06F9/321

摘要： A method and apparatus for trace data alignment for trace data generated during differing instruction pipeline stages selectively delays write data, memory access address and memory access control data zero, one or two pipeline stages dependent upon the memory access control data. Program counter data delayed by one clock cycle is delayed one pipeline stage if the next instruction is a new instruction. Program counter control data is also delayed one pipeline stage. The write data, memory access address, memory access control data, program counter data and program counter control data are further delayed a number of pipeline stages to align with read data. The program counter data holds if the pipeline is stalled. The write data, memory access address, memory access control data, program counter data and program counter control data holds in the multistage pipeline delay register if the pipeline is stalled.

摘要翻译： 用于在不同指令流水线阶段期间生成的跟踪数据的跟踪数据对准的方法和装置有选择地将写入数据，存储器访问地址和存储器访问控制数据零延迟，取决于存储器访问控制数据的一个或两个流水线级。 如果下一条指令是新指令，延迟一个时钟周期的程序计数器数据被延迟一个流水线级。 程序计数器控制数据也在一个流水线阶段被延迟。 写入数据，存储器访问地址，存储器访问控制数据，程序计数器数据和程序计数器控制数据进一步延迟了多个流水线级以与读取数据对准。 如果管道停滞，则程序计数器数据保持。 如果管道停滞，写入数据，存储器访问地址，存储器访问控制数据，程序计数器数据和程序计数器控制数据保持在多级流水线延迟寄存器中。