发明申请
- 专利标题: Semiconductor integrated circuit device and error checking and correcting method thereof
- 专利标题(中): 半导体集成电路器件及其误差校正和校正方法
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申请号: US10878229申请日: 2004-06-29
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公开(公告)号: US20050005230A1公开(公告)日: 2005-01-06
- 发明人: Mitsuhiro Koga , Hiroshi Shinya
- 申请人: Mitsuhiro Koga , Hiroshi Shinya
- 优先权: JP2003-188710 20030630
- 主分类号: G06F11/10
- IPC分类号: G06F11/10 ; G06F7/02 ; G06F11/00 ; G11C7/10 ; G11C11/401 ; G11C11/403 ; G11C11/406 ; G11C11/4096 ; G11C29/00 ; G11C29/42 ; H03M13/00 ; H03M13/09
摘要:
A semiconductor integrated circuit device includes a memory cell array, an error checking and correcting (ECC) circuit which performs an error checking and correcting operation for readout data read out from the normal data storing portion at data readout time during read latency and an I/O buffer. The memory cell array includes a normal data storing portion and a parity data storing portion. The normal data storing portion stores data for use in a normal data write and a normal data read. The parity data storing portion stores parity data for use in error checking and correcting. The EEC circuit carries out error checking and correcting read data read out from the normal data storing portion, during read latency cycle at a data read operation. The I/O buffer outputs the read data error checked and corrected by the ECC circuit, after the read latency cycle has lapsed.