公开(公告)号：US20240355405A1

公开(公告)日：2024-10-24

申请号：US18469562

申请日：2023-09-19

申请人： SK hynix Inc.

发明人： Jae Yong SON ,  Nam Kyeong KIM

IPC分类号： G11C29/12 ,  G11C29/18 ,  G11C29/42

CPC分类号： G11C29/1201 ,  G11C29/18 ,  G11C29/42 ,  G11C2029/1202

摘要： A read retry table (RRT) apparatus is coupled to a plurality of memory dies via a data path. The apparatus is configured to collect data from a plurality of memory cells coupled to a plurality of word lines in the plurality of memory dies via the data path; perform a first clustering on the plurality of word lines based on an error correction capability of error correction circuitry for collected data; perform a second clustering on an outlier of the first clustering; and generate or update an RRT based on values obtained from the first clustering and the second clustering.

公开(公告)号：US12124329B2

公开(公告)日：2024-10-22

申请号：US18211472

申请日：2023-06-19

申请人： Micron Technology, Inc.

发明人： Peter Mayer ,  Thomas Hein ,  Martin Brox ,  Wolfgang Anton Spirkl ,  Michael Dieter Richter

IPC分类号： G06F11/10 ,  G11C29/42

CPC分类号： G06F11/1044 ,  G06F11/1016 ,  G06F11/1028 ,  G11C29/42

摘要： Systems, apparatuses, and methods for transmission failure feedback associated with a memory device are described. A memory device may detect errors in received data and transmit an indication of the error when detected. The memory device may receive data and checksum information for the data from a controller. The memory device may generate a checksum for the received data and may detect transmission errors. The memory device may transmit an indication of detected errors to the controller, and the indication may be transmitted using a line that is different than an error detection code (EDC) line. A low-speed tracking clock signal may also be transmitted by the memory device over a line different than the EDC line. The memory device may transmit a generated checksum to the controller with a time offset applied to the checksum signaled over the EDC line.

公开(公告)号：US20240338215A1

公开(公告)日：2024-10-10

申请号：US18745042

申请日：2024-06-17

申请人： SK hynix Inc.

发明人： Dong Uk LEE ,  Seung Gyu JEONG ,  Dong Ha JUNG

IPC分类号： G06F9/30 ,  G06F9/48 ,  G06F12/02 ,  G06F12/0882 ,  G06F13/16 ,  G11C5/02 ,  G11C11/4093 ,  G11C29/42 ,  G11C29/44

CPC分类号： G06F9/30047 ,  G06F9/4818 ,  G06F12/0246 ,  G06F12/0882 ,  G06F13/1663 ,  G11C5/025 ,  G11C11/4093 ,  G11C29/42 ,  G11C29/44

摘要： A data processing system includes a compute blade generating a write command to store data and a read command to read the data, and a memory blade. The compute blade has a memory that stores information about performance characteristics of each of a plurality of memories, and determines priority information through which eviction of a cache line is carried out based on the stored information.

公开(公告)号：US20240312550A1

公开(公告)日：2024-09-19

申请号：US18598899

申请日：2024-03-07

申请人： Micron Technology, Inc.

发明人： Sujeet Ayyapureddi

IPC分类号： G11C29/42

CPC分类号： G11C29/42

摘要： Per-row recent and/or baseline error information for word lines may be stored along the word lines in some examples. In some examples, baseline error information may be stored in a fuse array. In some examples, the baseline error information may be loaded from the fuse array to a memory array. In some examples, based on the recent and/or baseline error information, the memory device may provide a post-package repair recommendation.

公开(公告)号：US12094551B2

公开(公告)日：2024-09-17

申请号：US17133810

申请日：2020-12-24

申请人： Intel Corporation

发明人： Hwa Chaw Law ,  Yu Ying Ong

IPC分类号： G11C29/42 ,  G11C29/00 ,  G11C29/12 ,  G11C29/44

CPC分类号： G11C29/42 ,  G11C29/1201 ,  G11C29/44 ,  G11C29/78

摘要： A modular Error Correction Code (ECC) scheme in a multi-channel IO link of an integrated circuit device is provided. The integrated circuit device may include core logic circuitry that may be configured after manufacturing. To accommodate the resulting variation, the modular ECC scheme may allow for partitioning a parity check matrix associated with the configuration of the core logic and peripheries coupled to the core logic. The parity check matrix is partitioned into smaller block matrices that is programmable. Multiple ECC modules corresponding to the block matrices are used to provide error detection and correction in the multi-channel IO link. The modular ECC scheme combined with programmable matrices (configurability) enables multi-channel IO link to be flexible to form different IO topologies.

公开(公告)号：US12088323B2

公开(公告)日：2024-09-10

申请号：US18254377

申请日：2020-11-25

申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

发明人： Qi Wang ,  Yiyang Jiang ,  Qianhui Li ,  Zongliang Huo ,  Tianchun Ye

IPC分类号： H03M13/39 ,  G11C29/12 ,  G11C29/42 ,  G11C29/46

CPC分类号： H03M13/3905 ,  G11C29/1201 ,  G11C29/42 ,  G11C29/46

摘要： A read-write method includes: sequentially writing, in a first direction, a code word obtained by information-bit encoding into a target memory cell in each layer of memory cell array in the three-dimensional memory; randomly reading the target memory cell in each layer of memory cell array, or sequentially reading the target memory cell in each layer of memory cell array in a second direction; and determining an LLR value of a current target memory cell according to a storage time corresponding to the current target memory cell when reading, a threshold voltage partition corresponding to the current target memory cell when reading, a comprehensive distribution state corresponding to the current target memory cell when reading, and a pre-established LLR table, so as to perform a soft decoding operation on the code word in the current target memory cell based on the LLR value of the current target memory cell.

公开(公告)号：US12079488B2

公开(公告)日：2024-09-03

申请号：US18050585

申请日：2022-10-28

申请人： Samsung Electronics Co., Ltd.

发明人： Jehyun Park ,  Kwanho Kim

IPC分类号： G06F12/00 ,  G06F3/06 ,  G06F11/07 ,  G06F11/10 ,  G11C29/42

CPC分类号： G06F3/0619 ,  G06F3/0653 ,  G06F3/0673 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/1048 ,  G11C29/42

摘要： A memory system includes a semiconductor memory device and a memory controller configured to control the semiconductor memory device. The semiconductor memory device includes a memory cell array including a plurality of memory cells configured to store data, a refresh controller configured to control a refresh operation with respect to the plurality of memory cells, and an error monitoring circuit configured to generate error information by monitoring an error in the data stored in the memory cell array based on refresh sensing data provided from the memory cell array during the refresh operation. The memory controller includes an error correction code (ECC) circuit and is further configured to correct the error in the data stored in the memory cell array using the ECC circuit based on the error information.

公开(公告)号：US20240290411A1

公开(公告)日：2024-08-29

申请号：US18597454

申请日：2024-03-06

申请人： Micron Technology, Inc.

发明人： Chun S. Yeung ,  Deping He ,  Jonathan S. Parry

IPC分类号： G11C29/42 ,  G11C7/04 ,  G11C29/12 ,  G11C29/44

CPC分类号： G11C29/42 ,  G11C7/04 ,  G11C29/1201 ,  G11C29/4401 ,  G11C2029/1202 ,  G11C2029/1204

摘要： Methods, systems, and devices for topology-based retirement in a memory system are described. In some examples, a memory system or memory device may be configured to evaluate error conditions relative to a physical or electrical organization of a memory array, which may support inferring the presence or absence of defects in one or more structures of a memory device. For example, based on various evaluations of detected errors, a memory system or a memory device may be able to infer a presence of a short-circuit, an open circuit, a dielectric breakdown, or other defects of a memory array that may be related to wear or degradation over time, and retire a portion of a memory array based on such an inference.

公开(公告)号：US12073217B2

公开(公告)日：2024-08-27

申请号：US18061370

申请日：2022-12-02

申请人： SK hynix Inc.

发明人： Dong Uk Lee ,  Seung Gyu Jeong ,  Dong Ha Jung

IPC分类号： G06F9/30 ,  G06F9/48 ,  G06F12/02 ,  G06F12/0882 ,  G06F13/16 ,  G11C5/02 ,  G11C11/4093 ,  G11C29/42 ,  G11C29/44

CPC分类号： G06F9/30047 ,  G06F9/4818 ,  G06F12/0246 ,  G06F12/0882 ,  G06F13/1663 ,  G11C5/025 ,  G11C11/4093 ,  G11C29/42 ,  G11C29/44

摘要： A data processing system includes a compute blade generating a write command to store data and a read command to read the data, and a memory blade. The compute blade has a memory that stores information about performance characteristics of each of a plurality of memories, and determines priority information through which eviction of a cache line is carried out based on the stored information.

公开(公告)号：US20240257893A1

公开(公告)日：2024-08-01

申请号：US18424922

申请日：2024-01-29

申请人： Infineon Technologies AG

发明人： Thomas Kern ,  Alexander Klockmann ,  Michael Goessel

IPC分类号： G11C29/42

CPC分类号： G11C29/42

摘要： Solutions are proposed related to error detection wherein (i) each byte of a second byte sequence is determined as a function of at least one byte of a first byte sequence, (ii) a byte of the second byte sequence is impermissible if it is not equal to an assigned byte of the first byte sequence and if no error of a predefined error set corrupts this byte to the assigned byte of the first byte sequence, and (iii) at least one error is detected if the second byte sequence is impermissible, the second byte sequence being impermissible if at least one byte of the second byte sequence is impermissible.