发明申请
US20050035798A1 Circuit, apparatus and method for obtaining a lock state value
失效
用于获得锁定状态值的电路,装置和方法
- 专利标题: Circuit, apparatus and method for obtaining a lock state value
- 专利标题(中): 用于获得锁定状态值的电路,装置和方法
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申请号: US10638857申请日: 2003-08-11
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公开(公告)号: US20050035798A1公开(公告)日: 2005-02-17
- 发明人: Scott Best
- 申请人: Scott Best
- 主分类号: H03L7/06
- IPC分类号: H03L7/06 ; H03L7/089 ; H03L7/095
摘要:
A circuit, apparatus and method provides a lock state value representing an amount of time a phase alignment circuit (“PAC”), such as a PLL or DLL, is tracking or locked to an incoming reference signal for a predetermined period of time. In an embodiment of the present invention, a lock state detection circuit is coupled to a lock loop circuit and includes a phase detection circuit and a counter circuit. The phase detection circuit includes a phase detector and delay elements that are coupled to the PAC phase detector. The phase detector outputs a lock state sample value of the PAC. In an embodiment of the present invention, the PAC is locked when a stream of alternating lock state sample values, logical 1's and 0's, are output from the phase detector. The counter circuit includes a flip-flop, an XOR gate and counter for obtaining a lock state value for a predetermined period of time.