The invention relates to a semiconductor memory module having a plurality of memory chips arranged next to one another in a row. The memory module has a module-internal clock, command/address and data bus which transfers clock signal, command and address signals and also data signals from a memory controller device to the memory chips and data signals from the memory chips to the memory controller device. The memory module has respective clock, command/address and data signal lines. The clock signal lines comprise two differential clock signal lines which, at their end opposite to the memory controller device are either open or connected to one another by a short-circuiting bridge. The memory chips, during a write operation, synchronize the write data with the clock signal running from the memory controller device to the end of the clock signal line and, during a read operation, output the read data synchronously with the clock signal reflected from the open or short-circuited end of the clock signal lines.