Invention Application
US20050041520A1 Semiconductor memory device 失效
半导体存储器件

Semiconductor memory device
Abstract:
A semiconductor memory device adapted for avoiding collision between the selection period of a word line for a refresh and the selection period of a word line for a read/write, comprises a cell array including a plurality of memory cells that require refreshing for retention of storage data and means for exercising control so that when a read/write request is input in a clock cycle following a clock cycle for performing a refresh operation, a read/write operation in the cell array is delayed by at least one clock cycle, and the read/write operation is started after completion of the refresh.
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