公开(公告)号：US07684270B2

公开(公告)日：2010-03-23

申请号：US11892488

申请日：2007-08-23

申请人： Takuya Hirota ,  Takao Yanagida ,  Hiroyuki Takahashi

发明人： Takuya Hirota ,  Takao Yanagida ,  Hiroyuki Takahashi

IPC分类号： G11C7/02

CPC分类号： G11C11/4094 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2281

摘要： In a conventional equalizer circuit, in an equalizing operation for setting voltages of a wiring pair having a predetermined voltage difference therebetween to be the same, it takes a long time to make the voltages of the wirings in a pair converge to a voltage having an offset with respect to a midpoint voltage of the voltages of the wiring pair after the equalizing operation. According to an equalizer circuit of the present invention, provided is an equalizer circuit (50) which sets the voltages of a first wiring (SAP) and a second wiring (SAN) to be substantially the same and which has a first transistor (N1) connected between the first wiring (SAP) and a first power supply circuit (for example, HVDD−Va) and a second transistor (N2) connected between the first wiring SAP and the second wiring (SAN). The equalizer circuit 50 makes the first transistor (N1) conductive, and then makes the second transistor (N2) conductive.

摘要翻译： 在传统的均衡器电路中，在将具有预定电压差的布线对的电压设定为相同的均衡操作中，使配线的电压成对地收敛到具有偏移的电压需要很长时间 相对于均衡动作后的配线对的电压的中点电压。 根据本发明的均衡器电路，提供了将第一布线（SAP）和第二布线（SAN）的电压设置为基本相同的并具有第一晶体管（N1）的均衡器电路（50） 连接在第一布线（SAP）和连接在第一布线SAP和第二布线（SAN）之间的第一电源电路（例如，HVDD-Va）和第二晶体管（N2）之间。 均衡器电路50使第一晶体管（N1）导通，然后使第二晶体管（N2）导通。

公开(公告)号：US07663945B2

公开(公告)日：2010-02-16

申请号：US11907442

申请日：2007-10-12

申请人： Hiroyuki Takahashi ,  Takuya Hirota ,  Atsushi Nakagawa

发明人： Hiroyuki Takahashi ,  Takuya Hirota ,  Atsushi Nakagawa

IPC分类号： G11C7/22 ,  G11C8/18

CPC分类号： G11C5/145 ,  G11C5/147 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227 ,  H03K5/133

摘要： A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.

摘要翻译： 电池芯单元及其外围电路由相对低压的电源驱动。 提供不依赖于电源电压的恒定电压作为提供给单元芯单元的字线的控制信号的升压电压（VBOOST）。 读出放大器将位线的较高电压电平放大到电源电压。 然后，用于产生用于定义从外围电路到小区核心单元的控制信号的转变定时和/或脉冲宽度的信号的电路使用具有延迟时间减小的特性的延迟电路来执行信号延迟， 降低所提供的电源电压。

公开(公告)号：US07489576B2

公开(公告)日：2009-02-10

申请号：US11723830

申请日：2007-03-22

申请人： Takuya Hirota ,  Takao Yanagida

发明人： Takuya Hirota ,  Takao Yanagida

IPC分类号： G11C7/02

CPC分类号： G11C7/12 ,  G11C7/02 ,  G11C7/08 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/005 ,  G11C2207/065

摘要： A semiconductor storage device has first and second cell arrays including a plurality of memory cells to store data, a sense amplifier selectively connected with either one of the first and second cell arrays, a first precharge circuit to set a pair of bit lines in the first cell array to a predetermined voltage, a second precharge circuit to set a pair of bit lines in the second cell array to a predetermined voltage, a first switch circuit to connect the sense amplifier with the first cell array, a second switch circuit to connect the sense amplifier with the second cell array, and a switch controller to control conductive state of the first and second switch circuits. In non-selection state where the sense amplifier does not access any of the cell arrays, the switch controller controls one of the switch circuits into conducting state.

摘要翻译： 一种半导体存储装置具有包括存储数据的多个存储单元的第一和第二单元阵列，选择性地与第一和第二单元阵列中的任一个连接的读出放大器，第一预充电电路，用于在第一和第二单元阵列中设置一对位线 单元阵列到预定电压，第二预充电电路，用于将第二单元阵列中的一对位线设置为预定电压;第一开关电路，用于将读出放大器与第一单元阵列连接;第二开关电路， 具有第二单元阵列的读出放大器和用于控制第一和第二开关电路的导通状态的开关控制器。 在非选择状态，其中读出放大器不访问任何单元阵列，开关控制器将开关电路之一控制为导通状态。

公开(公告)号：US07301830B2

公开(公告)日：2007-11-27

申请号：US10507117

申请日：2004-09-10

申请人： Hiroyuki Takahashi ,  Takuya Hirota ,  Atsushi Nakagawa

发明人： Hiroyuki Takahashi ,  Takuya Hirota ,  Atsushi Nakagawa

IPC分类号： G11C11/4074 ,  G11C11/4076 ,  G11C11/4063 ,  G11C7/22 ,  G11C8/18 ,  G11C8/08 ,  G11C7/12

CPC分类号： G11C5/145 ,  G11C5/147 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227 ,  H03K5/133

摘要： A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.

摘要翻译： 电池芯单元及其外围电路由相对低压的电源驱动。 提供不依赖于电源电压的恒定电压作为提供给单元芯单元的字线的控制信号的升压电压（VBOOST）。 读出放大器将位线的较高电压电平放大到电源电压。 然后，用于产生用于定义从外围电路到小区核心单元的控制信号的转变定时和/或脉冲宽度的信号的电路使用具有延迟时间减小的特性的延迟电路来执行信号延迟， 降低所提供的电源电压。

公开(公告)号：US07277344B2

公开(公告)日：2007-10-02

申请号：US11360593

申请日：2006-02-24

申请人： Hiroyuki Takahashi ,  Takuya Hirota

发明人： Hiroyuki Takahashi ,  Takuya Hirota

IPC分类号： G11C7/00

CPC分类号： G11C11/40615 ,  G11C11/406 ,  G11C2211/4061 ,  G11C2211/4067

摘要： A semiconductor storage device according to an embodiment of the present invention includes: a plurality of word lines; a plurality of memory cells corresponding to the plurality of word lines; and a refresh circuit for sequentially driving the plurality of word lines to refresh each of the plurality of memory cells based on a timer period, which sets the timer period in accordance with a disturb amount in an active mode upon shift from the active mode to the standby mode.

摘要翻译： 根据本发明实施例的半导体存储装置包括：多个字线; 与所述多个字线对应的多个存储单元; 以及刷新电路，用于根据定时器周期顺序驱动多个字线以刷新每个多个存储单元，该定时器周期根据从活动模式转换到活动模式时的活动模式中的干扰量来设置定时器周期 待机模式。

公开(公告)号：US07184322B2

公开(公告)日：2007-02-27

申请号：US10985876

申请日：2004-11-12

申请人： Hiroyuki Takahashi ,  Takato Shimoyama ,  Takuya Hirota

发明人： Hiroyuki Takahashi ,  Takato Shimoyama ,  Takuya Hirota

IPC分类号： G11C7/10 ,  G11C8/00

CPC分类号： G11C5/066

摘要： A semiconductor memory device has common terminals shared between a part or all of address terminals for receiving n bits of an address signal and data terminals for outputting a data signal with its bit width of n bits or less and dedicated address terminals for receiving m bits of the address signal, wherein at the time of a read, after the n bits of the address signal have been input, a plurality of data signals within a selected page are consecutively read out through the common terminals using the m bits of the address signal input from the dedicated address terminals.

摘要翻译： 半导体存储器件具有用于接收地址信号的n位的一部分或所有地址端之间的公共端子，以及用于输出其位宽为n位或更少的数据信号的数据端，以及用于接收m位的专用地址端 地址信号，其中在读取时，在输入了地址信号的n位之后，通过地址信号输入的m位，通过公共端连续地读出选定页内的多个数据信号 从专用地址终端。

公开(公告)号：US06944081B2

公开(公告)日：2005-09-13

申请号：US10363298

申请日：2001-08-30

申请人： Hiroyuki Takahashi ,  Atsushi Nakagawa ,  Yoshiyuki Katou ,  Hideo Inaba ,  Noriaki Komatsu ,  Takuya Hirota ,  Masahiro Yoshida

发明人： Hiroyuki Takahashi ,  Atsushi Nakagawa ,  Yoshiyuki Katou ,  Hideo Inaba ,  Noriaki Komatsu ,  Takuya Hirota ,  Masahiro Yoshida

IPC分类号： G11C11/406 ,  G11C7/00

CPC分类号： G11C11/406

摘要： A semiconductor memory device capable of a further reduction in power consumption for refresh operation is provided. Cell arrays S0, S1 are divided into respective four blocks B0˜B3 and B10˜B13. In a normal read/write operation, by address data designating a word line, one of the cell arrays is selected, and also one block is selected in the selected cell array, and further one word line is selected in the selected block. In a refresh operation, one of the cell arrays is selected, and four blocks in the selected cell array are simultaneously refreshed. Namely, respective one word line is selected from each of the four blocks, and the selected word lines are refreshed, thereby to reduce a power comsumption as compared to when the plural cell arrays are refreshed.

摘要翻译： 提供能够进一步降低刷新操作的功耗的半导体存储器件。 单元阵列S 0，S 1被分成四个块B 0〜B 3和B 10〜B 13。 在通常的读/写操作中，通过指定字线的地址数据，选择单元阵列中的一个，并且在所选择的单元阵列中选择一个块，并且在所选块中还选择一个字线。 在刷新操作中，选择单元阵列之一，同时刷新所选单元阵列中的四个块。 也就是说，从四个块中的每一个中选择相应的一个字线，并且与多个单元阵列刷新时相比，刷新所选择的字线，从而降低功耗。

公开(公告)号：US06201308B1

公开(公告)日：2001-03-13

申请号：US09153384

申请日：1998-09-15

申请人： Kayoko Ikegami ,  Takuya Hirota

发明人： Kayoko Ikegami ,  Takuya Hirota

IPC分类号： H01L2348

CPC分类号： H01L23/5286 ,  H01L24/06 ,  H01L27/0207

摘要： A semiconductor chip has a first ground line for maintaining a stable ground potential for the internal circuit. The first ground line is connected to a second ground line disposed on a scribe region of the semiconductor chip via a bonding pad, which is connected to an external lead frame. I/O circuit has a third ground line directly connected to the second ground line without passing the bonding pad. The noise propagated from the third ground line to the first ground line is reduced by passing the noise through the bonding pad.

摘要翻译： 半导体芯片具有用于保持内部电路的稳定接地电位的第一接地线。 第一接地线经由与外部引线框连接的接合焊盘连接到设置在半导体芯片的划线区域上的第二接地线。 I / O电路具有直接连接到第二接地线的第三接地线，而不通过接合焊盘。 从第三地线传播到第一地线的噪声通过将粘合垫通过噪声来减少。

公开(公告)号：US20090016123A1

公开(公告)日：2009-01-15

申请号：US12168986

申请日：2008-07-08

申请人： Takao Yanagida ,  Takuya Hirota

发明人： Takao Yanagida ,  Takuya Hirota

IPC分类号： G11C7/00

CPC分类号： G11C11/4076 ,  G11C7/1006 ,  G11C7/1009 ,  G11C11/4096

摘要： A semiconductor device (DRAM) according to one embodiment of the present invention includes a plurality of pairs of digit lines (digit True, Not) connected to a memory cell, a common signal line pair (main I/O True, Not) connected to the plurality of pairs of digit lines in common, a main I/O equalizer performing precharge of the common signal line pair, and a control circuit determining whether the precharge operation is continued irrespective of a signal level of a mask signal input from an outside.

摘要翻译： 根据本发明的一个实施例的半导体器件（DRAM）包括连接到存储器单元的多对数字线（数字True，Not），连接到存储单元的公共信号线对（主I / O True，否） 多个数字线对，主I / O均衡器，执行公共信号线对的预充电，以及控制电路，确定预充电操作是否继续，而与外部输入的屏蔽信号的信号电平无关。

公开(公告)号：US07466609B2

公开(公告)日：2008-12-16

申请号：US11882230

申请日：2007-07-31

申请人： Hiroyuki Takahashi ,  Takuya Hirota ,  Atsushi Nakagawa

发明人： Hiroyuki Takahashi ,  Takuya Hirota ,  Atsushi Nakagawa

IPC分类号： G11C7/22 ,  G11C8/18 ,  G11C8/08 ,  G11C5/14 ,  G11C7/12

CPC分类号： G11C5/145 ,  G11C5/147 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227 ,  H03K5/133

摘要： A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.

摘要翻译： 电池芯单元及其外围电路由相对低压的电源驱动。 提供不依赖于电源电压的恒定电压作为提供给单元芯单元的字线的控制信号的升压电压（VBOOST）。 读出放大器将位线的较高电压电平放大到电源电压。 然后，用于产生用于定义从外围电路到小区核心单元的控制信号的转变定时和/或脉冲宽度的信号的电路使用具有延迟时间减小的特性的延迟电路来执行信号延迟， 降低所提供的电源电压。