发明申请
US20050048766A1 METHOD FOR FABRICATING A CONDUCTIVE PLUG IN INTEGRATED CIRCUIT
审中-公开
在集成电路中制作导电插片的方法
- 专利标题: METHOD FOR FABRICATING A CONDUCTIVE PLUG IN INTEGRATED CIRCUIT
- 专利标题(中): 在集成电路中制作导电插片的方法
-
申请号: US10605007申请日: 2003-08-31
-
公开(公告)号: US20050048766A1公开(公告)日: 2005-03-03
- 发明人: Wen-Chieh Wu , Yi-Nan Chen , Chun-Yi Wu
- 申请人: Wen-Chieh Wu , Yi-Nan Chen , Chun-Yi Wu
- 主分类号: H01L21/285
- IPC分类号: H01L21/285 ; H01L21/768 ; H01L21/4763 ; H01L21/22 ; H01L21/38 ; H01L21/44
摘要:
A method for fabricating a conductive plug device is disclosed. A semiconductor substrate having a diffusion region thereon is provided. A dielectric layer is deposited over the semiconductor substrate. An opening is formed in the dielectric layer to expose a portion of the diffusion region. An un-doped CVD silicon layer is deposited on interior walls of the opening. A pure CVD phosphorus layer is in-situ deposited on the un-doped CVD silicon layer. The pure CVD phosphorus layer thereafter diffuses into the subjacent un-doped CVD silicon layer to form a doped silicon layer. Subsequently, a second un-doped CVD silicon layer is in-situ deposited on the doped silicon layer.
信息查询
IPC分类: