发明申请
- 专利标题: Data stream frequency reduction and/or phase shift
- 专利标题(中): 数据流频率降低和/或相移
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申请号: US10656195申请日: 2003-09-04
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公开(公告)号: US20050053182A1公开(公告)日: 2005-03-10
- 发明人: Alexander Andreev , Igor Vikhliantsev , Vojislav Vukovic
- 申请人: Alexander Andreev , Igor Vikhliantsev , Vojislav Vukovic
- 申请人地址: US CA Milpitas
- 专利权人: LSI Logic Corporation
- 当前专利权人: LSI Logic Corporation
- 当前专利权人地址: US CA Milpitas
- 主分类号: H03M9/00
- IPC分类号: H03M9/00 ; H04L7/02 ; H04L7/00
摘要:
A frequency reduction or phase shifting circuit has an input receiving an input data stream having an input frequency and a representation of desired output frequency. A splitter splits the input data stream into a plurality of split signals each at a frequency of the desired output frequency. A plurality of catchers identify valid bits of each respective split signal. A shifter shifts valid bits identified by at least some of the catchers by a predetermined number which establishes a de-serialization level for frequency reduction or phase shifting. An output provide an output data stream at the desired output frequency.
公开/授权文献
- US07313660B2 Data stream frequency reduction and/or phase shift 公开/授权日:2007-12-25
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