公开(公告)号：US08044437B1

公开(公告)日：2011-10-25

申请号：US11130350

申请日：2005-05-16

申请人： Ramnath Venkatraman ,  Carl Anthony Monzel, III ,  Subramanian Ramesh

发明人： Ramnath Venkatraman ,  Carl Anthony Monzel, III ,  Subramanian Ramesh

IPC分类号： H01L27/118

CPC分类号： H01L27/1104 ,  G11C8/16 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/11807 ,  H03K19/1733 ,  Y10S257/903

摘要： An improved integrated circuit cell architecture is provided for configurability between a memory cell or logic elements. The cell architecture is configured on variable layers above a first layer of metal, with the first layer of metal and layers therebelow reserved as fixed layers. By coupling a maximum of two layout cells together, a single-port or dual-port memory cell is realized. Likewise, by interconnecting transistors within a single cell or transistors among two or more cells, a logic device is realized. Within each cell, the bit lines are arranged on a layer separate from the wordlines, and extend orthogonal to each other.

摘要翻译： 提供了一种改进的集成电路单元架构，用于存储单元或逻辑元件之间的可配置性。 单元架构配置在第一金属层上方的可变层上，其中第一层金属和层保留为固定层。 通过将最多两个布局单元耦合在一起，实现单端口或双端口存储单元。 同样，通过将单个单元内的晶体管或两个或更多个单元之间的晶体管互连，实现逻辑器件。 在每个单元内，位线布置在与字线分开的层上，并且彼此正交延伸。

公开(公告)号：US08043968B2

公开(公告)日：2011-10-25

申请号：US12764004

申请日：2010-04-20

申请人： Hao Cui ,  Peter A. Burke ,  Wilbur G. Catabay

发明人： Hao Cui ,  Peter A. Burke ,  Wilbur G. Catabay

IPC分类号： H01L21/00

CPC分类号： H01L21/76832 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76883

摘要： Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.

摘要翻译： 本发明的实施例包括具有增加的电迁移寿命的铜互连结构。 这种结构可以包括其上形成有铜层的半导体衬底。 在铜层上形成介电阻挡层叠体。 电介质势垒叠层包括邻近铜层形成的第一部分和形成在第一部分上的第二部分，第一部分具有相对于第二部分提高的对铜的粘附性，并且两个部分形成为具有耐铜扩散性。 本发明还包括用于构造这种结构的几个实施例。 可以通过等离子体处理或离子注入电介质阻挡层的选定部分与粘合增强材料来增加电介质阻挡层与铜的附着，以增加堆叠中这种材料的浓度。

公开(公告)号：US07760578B2

公开(公告)日：2010-07-20

申请号：US12254421

申请日：2008-10-20

申请人： David Vinke ,  Michael N. Dillon ,  Bret Alan Oeltjen ,  Uday Anumalachetty ,  Thomas Mathews Antisseril

发明人： David Vinke ,  Michael N. Dillon ,  Bret Alan Oeltjen ,  Uday Anumalachetty ,  Thomas Mathews Antisseril

IPC分类号： G11C5/14

CPC分类号： G11C5/063 ,  G11C8/10 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00

摘要： An integrated circuit structure for distributing power to one or more standard cells in an integrated circuit includes a first plurality of standard cells and a power mesh power connection structure coupled to the cells. Each of the standard cells includes first and second power rails adapted for connection to a voltage supply and a voltage return, respectively, of the standard cells. Each standard cell in a subset of the standard cells is arranged in direct abutment with at least two other standard cells, and at least first and second end cells are arranged in direct abutment with at least one other standard cell of the first plurality of standard cells. The power mesh power connection structure includes a plurality of conductive elements formed in a plurality of different conductive layers in the integrated circuit. The power mesh power connection structure is operative to connect the first and second power rails of the first plurality of standard cells to the voltage supply and voltage return, respectively, and is configured so as to reduce a first voltage differential between respective first power rails of the standard cells and to reduce a second voltage differential between respective second power rails of the standard cells.

摘要翻译： 用于向集成电路中的一个或多个标准单元分配功率的集成电路结构包括耦合到该单元的第一多个标准单元和功率网格功率连接结构。 每个标准单元包括分别连接到标准单元的电压源和电压返回的第一和第二电源轨。 标准细胞子集中的每个标准细胞被布置成与至少两个其它标准细胞直接邻接，并且至少第一和第二末端细胞被布置成与第一多个标准细胞的至少一个其它标准细胞直接邻接 。 功率网格功率连接结构包括形成在集成电路中的多个不同导电层中的多个导电元件。 功率网格电力连接结构可操作以将第一多个标准单元的第一和第二电力轨分别连接到电压供应和电压返回，并且被配置为减少相应的第一电力轨之间的第一电压差 并且减小标准单元的相应的第二电源轨之间的第二电压差。

公开(公告)号：US07751609B1

公开(公告)日：2010-07-06

申请号：US09553140

申请日：2000-04-20

申请人： Michael J. Berman

发明人： Michael J. Berman

IPC分类号： G06K9/00

CPC分类号： H01L22/12 ,  B24B37/013 ,  B24B49/12 ,  H01L22/26

摘要： A method and apparatus is provided for determining thickness of films or layers during chemical-mechanical planarization/polishing (CMP) of a semiconductor substrate or wafer in situ. The method may be used to determine end-point during CMP especially of oxide films deposited on the substrate or wafer. In one embodiment, the method includes: a) capturing images of the surface of the substrate using high speed imaging; b) performing pattern recognition on the captured images; c) selecting one of the captured images based on the pattern recognition; and d) converting the selected image into a thickness measurement. In one form, the high speed imaging comprises a high speed camera, while in another form, the high speed imaging comprises a conventional camera and a laser pulse or flash tube. In yet another embodiment, reflective laser interference patterns of the substrate are captured and analyzed for interference pattern changes that can signal a practical end-point.

摘要翻译： 提供了一种方法和装置，用于在半导体衬底或晶片原位化学机械平面化/抛光（CMP）期间确定膜或层的厚度。 该方法可以用于确定CMP期间的终点，特别是在沉积在衬底或晶片上的氧化膜上。 在一个实施例中，该方法包括：a）使用高速成像技术拍摄基片表面的图像; b）对所捕获的图像执行模式识别; c）基于模式识别来选择所捕获的图像之一; 以及d）将所选择的图像转换成厚度测量。 在一种形式中，高速成像包括高速摄像机，而在另一种形式中，高速成像包括常规相机和激光脉冲或闪光管。 在另一个实施例中，捕获并分析了衬底的反射激光干涉图案，用于可以发出实际端点的干扰图案变化。

公开(公告)号：US07640461B2

公开(公告)日：2009-12-29

申请号：US11939573

申请日：2007-11-14

申请人： Thai-Minh Nguyen ,  William Shen ,  David Vinke ,  Christopher Coleman

发明人： Thai-Minh Nguyen ,  William Shen ,  David Vinke ,  Christopher Coleman

IPC分类号： G06K5/04 ,  G11B5/00 ,  G06F1/00

CPC分类号： G01R31/318594 ,  G01R31/318552 ,  G11C29/10 ,  G11C29/56 ,  G11C29/56004 ,  G11C29/56012 ,  G11C2029/3602

摘要： A clock pulse controller includes a test clock pulse input for receiving test clock pulses. A scan enable input receives a scan enable signal having a first state and a second state. A trigger pulse input receives a trigger pulse. A clock pulse output generates a launch clock pulse and a capture clock pulse from the test clock pulses immediately after receiving a predetermined number of the test clock pulses immediately following the trigger pulse. A delayed scan enable output generates a delayed scan enable signal that transitions from the first state to the second state between a leading edge of the launch clock pulse and a leading edge of the capture clock pulse.

摘要翻译： 时钟脉冲控制器包括用于接收测试时钟脉冲的测试时钟脉冲输入。 扫描使能输入接收具有第一状态和第二状态的扫描使能信号。 触发脉冲输入接收触发脉冲。 时钟脉冲输出在接收到紧跟在触发脉冲之后的预定数量的测试时钟脉冲之后立即从测试时钟脉冲产生启动时钟脉冲和捕获时钟脉冲。 延迟扫描使能输出产生延迟的扫描使能信号，其在启动时钟脉冲的前沿和捕获时钟脉冲的前沿之间从第一状态转换到第二状态。

公开(公告)号：US07577928B2

公开(公告)日：2009-08-18

申请号：US11376781

申请日：2006-03-15

申请人： Peter Lindberg ,  Richard K. Kirchner ,  Sandeep Bhutani

发明人： Peter Lindberg ,  Richard K. Kirchner ,  Sandeep Bhutani

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A system, apparatus and method for generating and validating extracted timing model files, such as macro library files, are disclosed. A user interface or data template is provided to an engineer that allows for the population of data within particular fields related to timing characteristics of an IP block, cell or core. An extracted timing model file is generated and a validation procedure is performed. This validation procedure may include comparing the information with the file to a test bench have a plurality of test points. In particular, data provided by the engineer is checked against multiple criteria to ensure that this data is valid and/or falls within an appropriate value range constraints. After the validation procedure has completed, the engineer is provided a summary of the validation results.

摘要翻译： 公开了一种用于生成和验证提取的定时模型文件（诸如宏库文件）的系统，装置和方法。 将用户界面或数据模板提供给允许在与IP块，单元或核心的定时特性相关的特定领域内的数据的总体的工程师。 生成提取的定时模型文件，并执行验证过程。 该验证过程可以包括将信息与文件进行比较，以具有多个测试点。 特别地，由多个标准检查由工程师提供的数据，以确保该数据有效和/或落入适当的值范围约束。 验证程序完成后，工程师将提供验证结果的摘要。

公开(公告)号：US07568216B2

公开(公告)日：2009-07-28

申请号：US10741559

申请日：2003-12-19

申请人： Andrew J. Spry ,  Kevin Lindgren ,  James Lynn

发明人： Andrew J. Spry ,  Kevin Lindgren ,  James Lynn

IPC分类号： H04L9/00

CPC分类号： H04L63/105 ,  H04L63/08 ,  H04L63/164

摘要： The present invention is directed to methods for defining and naming iSCSI targets using volume access and security policy. In an exemplary aspect of the present invention, a method for defining an iSCSI target using volume access and security policy may include the following steps. One or more volumes of a network entity may be first mapped to an initiator. The mapping defines the unique Logical Unit Number for the volume to an initiator. Then, a security level may be defined for access to each volume accessed by the initiator. The subset of mappings for each initiator may be given any unique name. Next, the mapping and security subsets may be used to define the fully qualified targets with which the initiator may open a session.

摘要翻译： 本发明涉及使用卷访问和安全策略来定义和命名iSCSI目标的方法。 在本发明的示例性方面，使用卷访问和安全策略定义iSCSI目标的方法可以包括以下步骤。 网络实体的一个或多个卷可以首先映射到发起者。 映射定义了启动器的卷的唯一逻辑单元号。 然后，可以定义访问由启动器访问的每个卷的安全级别。 每个启动器的映射子集可以被赋予任何唯一的名称。 接下来，映射和安全子集可以用于定义发起者可以通过该目标打开会话的完全限定目标。

公开(公告)号：US20090030660A1

公开(公告)日：2009-01-29

申请号：US11782393

申请日：2007-07-24

申请人： Zeki Celik ,  Atila Mertol

发明人： Zeki Celik ,  Atila Mertol

IPC分类号： G06F17/10

CPC分类号： G06F17/5018 ,  G06F2217/16 ,  G06F2217/40 ,  G06F2217/80 ,  G06T17/20 ,  G06T19/00 ,  H05K3/0005

摘要： A process is provided, which includes receiving geometrical information for a plurality of layers of an electronic structure within at least one output data file from an electronic structure design tool. At least one numerical analysis data file is created from the output data file, which contains the geometrical information and has a file structure compatible with a numerical analysis tool for characterizing the electronic structure. The numerical analysis tool is used to read the numerical analysis data file and generate a three-dimensional meshed geometric model of the electronic structure from the numerical analysis data file, wherein the model includes three-dimensional geometric models of each layer. The model can then be used, for example, to solve numerical thermal, mechanical or electrical equations that are applied to the model.

摘要翻译： 提供了一种过程，其包括从电子结构设计工具接收至少一个输出数据文件内的电子结构的多个层的几何信息。 从输出数据文件创建至少一个数值分析数据文件，该数据文件包含几何信息，并具有与用于表征电子结构的数值分析工具兼容的文件结构。 数值分析工具用于读取数值分析数据文件，并从数值分析数据文件生成电子结构的三维网格几何模型，其中模型包括每层三维几何模型。 然后可以使用该模型，例如，解决应用于模型的数值热，机械或电学方程。

公开(公告)号：US07480881B2

公开(公告)日：2009-01-20

申请号：US11465662

申请日：2006-08-18

申请人： Alexander Tetelbaum ,  Ruben Molina ,  Subodh Bhike

发明人： Alexander Tetelbaum ,  Ruben Molina ,  Subodh Bhike

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method and computer program for static timing analysis includes receiving as input minimum and maximum stage delays for two corners of an integrated circuit design. A path slack for a setup timing check is calculated from the minimum and maximum stage delays as a function of net clock cycle interval T_clk, launch path delay T_LP, capture path delay T_CP, data path delay T_DP, and a first delay de-rating factor Y1. A path slack for a hold timing check is calculated from the minimum and maximum stage delays as a function of the launch path delay T_LP, the capture path delay T_CP, the data path delay T_DP, and a second delay de-rating factor Y2. The path slack calculated for the setup timing check and for the hold timing check is generated as output.

摘要翻译： 用于静态时序分析的方法和计算机程序包括接收集成电路设计的两个角的最小和最大阶段延迟作为输入。 根据净时钟周期间隔T_clk，发射路径延迟T_LP，捕获路径延迟T_CP，数据路径延迟T_DP和第一延迟降额系数的函数，从最小和最大级延迟计算用于设置定时检查的路径松弛 Y1。 根据发射路径延迟T_LP，捕获路径延迟T_CP，数据路径延迟T_DP和第二延迟降额因子Y2的函数的最小和最大级延迟来计算用于保持定时检查的路径松弛。 产生用于设置定时检查和保持定时检查的路径松弛作为输出。

公开(公告)号：US20080270505A1

公开(公告)日：2008-10-30

申请号：US11741865

申请日：2007-04-30

申请人： Anatoli Bolotov ,  Mikhail I. Grinchuk

发明人： Anatoli Bolotov ,  Mikhail I. Grinchuk

IPC分类号： G06F7/00

CPC分类号： G06F7/724 ,  H04L9/0631 ,  H04L2209/122 ,  H04L2209/125

摘要： A combination of an infrequently-called tiny multiplication unit and a “differential” unit that quickly computes T (n+1) basing on known T n. The schedule (how often the multiplication unit is called) can be considered as a parameter of the algorithm. The proposed architecture of the “differential” unit is efficient both in terms of speed (delay) and area (gate count).

摘要翻译： 可以快速计算T mm“file =”US20080270505A1-20081030-P00001.TIF“img-content =”character“img-format =”tif“/> n。 调度（调用乘法单元的频率）可以被认为是算法的参数。 所提出的“差分”单元的架构在速度（延迟）和面积（门数）方面都是有效的。