Invention Application
- Patent Title: Memory expansion and integrated circuit stacking system and method
- Patent Title (中): 内存扩展和集成电路堆叠系统及方法
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Application No.: US10804452Application Date: 2004-03-19
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Publication No.: US20050057911A1Publication Date: 2005-03-17
- Inventor: Russell Rapport , James Cady , James Wilder , David Roper , James Wehrly , Jeff Buchle
- Applicant: Russell Rapport , James Cady , James Wilder , David Roper , James Wehrly , Jeff Buchle
- Assignee: Staktek Group, L.P.
- Current Assignee: Staktek Group, L.P.
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L25/10 ; H05K7/06 ; H01L23/538

Abstract:
The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment of the memory addressing system, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access.
Public/Granted literature
- US07542304B2 Memory expansion and integrated circuit stacking system and method Public/Granted day:2009-06-02
Information query
IPC分类: