公开(公告)号：US20090300912A1

公开(公告)日：2009-12-10

申请号：US12542503

申请日：2009-08-17

Applicant: John Thomas ,  Russell Rapport ,  Robert Washburn

Inventor： John Thomas ,  Russell Rapport ,  Robert Washburn

IPC: H05K3/30

CPC classification number: H05K1/0231 ,  H01G4/232 ,  H01G4/30 ,  H01G4/38 ,  H01L23/50 ,  H01L23/5387 ,  H01L2224/16 ,  H01L2924/15311 ,  H05K1/112 ,  H05K1/141 ,  H05K1/162 ,  H05K2201/049 ,  H05K2201/10734 ,  Y10T29/4913

Abstract: An apparatus and a method for adding capacitance while conserving circuit board surface area. An apparatus for adding capacitance while conserving circuit board surface area includes a flex capacitor circuit with an upper surface and a lower surface and a plurality of conductive layers and an integrated-circuit (IC) device mounted on to the upper surface of the flex capacitor circuit and electrically connected to the flex capacitor circuit. The flex capacitor circuit is configured to provide bypass capacitance and, therefore, adds capacitance to the IC device when the IC device is mounted on the flex capacitor circuit.

Abstract translation: 一种在节省电路板表面积的同时增加电容的装置和方法。 在保持电路板表面积的同时增加电容的装置包括具有上表面和下表面的柔性电容电路和多个导电层以及安装在柔性电容器电路的上表面上的集成电路（IC）装置 并电连接到柔性电容器电路。 柔性电容器电路被配置为提供旁路电容，并且因此当IC器件安装在柔性电容器电路上时，向IC器件增加电容。

公开(公告)号：US07542304B2

公开(公告)日：2009-06-02

申请号：US10804452

申请日：2004-03-19

Applicant: Russell Rapport ,  James W. Cady ,  James Wilder ,  David L. Roper ,  James Douglas Wehrly, Jr. ,  Jeff Buchle

Inventor： Russell Rapport ,  James W. Cady ,  James Wilder ,  David L. Roper ,  James Douglas Wehrly, Jr. ,  Jeff Buchle

IPC: H01R9/00

CPC classification number: H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/107 ,  H01L2924/3011 ,  H01L2924/00012

Abstract: The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment of the memory addressing system, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access.

Abstract translation: 本发明将集成电路（IC）堆叠成节省PWB或其他板表面积的模块。 在另一方面，本发明提供了一种较低电容存储器扩展寻址系统和方法，并且优选地具有本文提供的CSP堆叠模块。 在根据本发明的优选实施例中，形式标准提供了一种物理形式，其允许在广泛的CSP封装系列中发现的许多变化的封装尺寸在使用标准连接柔性电路设计时被有利地使用。 在优选实施例中，将设计形式标准，以便传热材料例如铜，以改善热性能。 在存储器寻址系统的优选实施例中，高速交换系统选择与堆叠模块的每个级别相关联的数据线，以减少对存储器访问中的数据信号的负载影响。

公开(公告)号：US06992501B2

公开(公告)日：2006-01-31

申请号：US10800816

申请日：2004-03-15

Applicant: Russell Rapport

Inventor： Russell Rapport

IPC: H03K19/003

CPC classification number: H04L25/0298

Abstract: A termination circuit changes impedance to match a transmission line impedance. The change is made after a signal driver applies a signal through the termination circuit to the transmission line but before a signal reflection returns from an end of the transmission line.

Abstract translation: 终端电路改变阻抗以匹配传输线阻抗。 在信号驱动器通过终端电路将信号施加到传输线之后，但在信号反射从传输线的末端返回之前进行改变。

公开(公告)号：US20060125067A1

公开(公告)日：2006-06-15

申请号：US11331969

申请日：2006-01-13

Applicant: James Wehrly ,  Paul Goodwin ,  Russell Rapport

Inventor： James Wehrly ,  Paul Goodwin ,  Russell Rapport

IPC: H01L23/02

CPC classification number: H05K1/189 ,  H05K1/0203 ,  H05K1/11 ,  H05K1/181 ,  H05K3/0061 ,  H05K2201/056 ,  H05K2201/09445 ,  H05K2201/10159 ,  H05K2201/1056 ,  H05K2201/10734 ,  H05K2203/1572

Abstract: Provided circuit modules employ flexible circuitry populated with integrated circuitry (ICs). The flex circuitry is disposed about a rigid substrate. Contacts distributed along the flexible circuitry provide connection between the module and an application environment. A strain relief portion of the flex circuitry has preferably fewer layers than the portion of the flex circuitry along which the integrated circuitry is disposed and may further may exhibit more flexibility than the portion of the flex circuit populated with integrated circuitry. The substrate form is preferably devised from thermally conductive materials.

公开(公告)号：US20060043558A1

公开(公告)日：2006-03-02

申请号：US10931828

申请日：2004-09-01

Applicant: James Cady ,  Russell Rapport ,  James Wilder

Inventor： James Cady ,  Russell Rapport ,  James Wilder

IPC: H01L23/02

CPC classification number: H01L25/105 ,  H01L23/4985 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: Abstract of the DisclosureIntegrated circuits (ICs) are stacked into modules that conserve PCB or other board surface area. The modules provide for lower capacitance memory signaling systems and methods for connecting stacked CSPs in a serial cascade arrangement. In one preferred embodiment, on-die terminations are used selectively to terminate a cascaded series of conductive paths. In another preferred embodiment, a form standard provides a physical form that allows many of the varying package sizes found in a broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design.

Abstract translation: 公开的摘要集成电路（IC）堆叠成模块以节省PCB或其他板表面积。 这些模块提供了较低电容存储器信号系统和用于以串联级联布置连接堆叠CSP的方法。 在一个优选实施例中，选择性地使用管芯端子来终止级联的导电路径。 在另一个优选实施例中，形式标准提供了一种物理形式，其允许在采用标准连接柔性电路设计的同时，在宽范围的CSP封装系列中发现许多变化的封装尺寸。

公开(公告)号：US20050200380A1

公开(公告)日：2005-09-15

申请号：US10800816

申请日：2004-03-15

Applicant: Russell Rapport

Inventor： Russell Rapport

IPC: H03K19/003

CPC classification number: H04L25/0298

Abstract: A termination circuit changes impedance to match a transmission line impedance. The change is made after a signal driver applies a signal through the termination circuit to the transmission line but before a signal reflection returns from an end of the transmission line.

Abstract translation: 终端电路改变阻抗以匹配传输线阻抗。 在信号驱动器通过终端电路将信号施加到传输线之后，但在信号反射从传输线的末端返回之前进行改变。

公开(公告)号：US06940729B2

公开(公告)日：2005-09-06

申请号：US10136890

申请日：2002-05-02

Applicant: James W. Cady ,  James Wilder ,  David L. Roper ,  Russell Rapport ,  James Douglas Wehrly, Jr. ,  Jeffrey Alan Buchle

Inventor： James W. Cady ,  James Wilder ,  David L. Roper ,  Russell Rapport ,  James Douglas Wehrly, Jr. ,  Jeffrey Alan Buchle

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36 ,  H05K7/10 ,  H05K7/12

CPC classification number: H01L23/49816 ,  H01L23/3114 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00012

Abstract: The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The invention provides techniques and structures for aggregating chip scale-packaged integrated circuits (CSPs) or leaded packages with other CSPs or with monolithic or stacked leaded packages into modules that conserve PWB or other board surface area. The present invention can be used to advantage with CSP or leaded packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element IC and a support element IC are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two IC elements. A portion of the flex circuit connected to the support element is folded over the base element to dispose the support element above the base element while reducing the overall footprint occupied by the two ICs. The flex circuit connects the ICs and provides a thermal and electrical connection path between the module and an application environment such as a printed wiring board (PWB). The present invention may be employed to advantage in numerous configurations and combinations in modules provided for high-density memories, high capacity computing, or applications where small size is valued.

Abstract translation: 本发明将封装的集成电路堆叠成节省PWB或其他板表面积的模块。 本发明提供了用于将芯片级封装集成电路（CSP）或具有其他CSP的引线封装或者将单片或堆叠引线封装集成到节省PWB或其他板表面积的模块中的技术和结构。 本发明可以用于具有各种尺寸和配置的CSP或带引线的封装，其范围从具有许多触点的较大封装的基底元件到较小的封装，例如诸如管芯尺寸的封装（例如DSBGA）。 在根据本发明设计的优选实施例中，基体元件IC和支撑元件IC通过具有图案化以选择性地连接两个IC元件的至少两个导电层的柔性电路聚集。 连接到支撑元件的柔性电路的一部分折叠在基座元件上，以将支撑元件设置在基座元件上方，同时减少两个IC所占据的总占地面积。 柔性电路连接IC，并在模块和诸如印刷电路板（PWB）的应用环境之间提供热和电连接路径。 本发明可用于为高密度存储器，高容量计算或小尺寸的应用提供的模块中的多种配置和组合中的优点。

公开(公告)号：US06914324B2

公开(公告)日：2005-07-05

申请号：US10453398

申请日：2003-06-03

Applicant: Russell Rapport ,  James W. Cady ,  James Wilder ,  David L. Roper ,  James Douglas Wehrly, Jr. ,  Jeff Buchle

Inventor： Russell Rapport ,  James W. Cady ,  James Wilder ,  David L. Roper ,  James Douglas Wehrly, Jr. ,  Jeff Buchle

IPC: H01L21/44 ,  H01L23/31 ,  H01L23/498 ,  H01L23/50 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36 ,  H01L23/02

CPC classification number: H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/50 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01055 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2224/0401

Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard is disposed between the flex circuitry and the IC package over which a portion of the flex circuitry is laid. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access. This favorably changes the impedance characteristics exhibited by a DIMM board populated with stacked modules. In a preferred embodiment, FET multiplexers for example, under logic control select particular data lines associated with particular levels of stacked modules populated upon a DIMM for connection to a controlling chip set in a memory expansion system.

公开(公告)号：US06404662B1

公开(公告)日：2002-06-11

申请号：US09646724

申请日：2001-03-07

Applicant: James W. Cady ,  Russell Rapport

Inventor： James W. Cady ,  Russell Rapport

IPC: G11C506

CPC classification number: G11C5/06 ,  G11C5/02 ,  G11C5/04 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: The RAMBUS compatible configuration of the present invention is achieved by stacking one of the two modules in the stacked configuration in an upside-down position with respect to the other. This way, the corresponding electrical leads of each memory module will extend on opposite sides of the stacked package and will be securably connected to vertical rails. The vertical rails are electrically and securably connected to the bonding pads which electrically connect to the RAMBUS signal channel. In this embodiment, the electrical leads of one memory module electrically connect to the signal channel at points located on one side of the stacked package and the electrical leads of the other memory module connect to the signal channel at points located on the opposite side of the stacked package. The resulting distance between the points of contact between corresponding leads of each memory module in the stacked package is sufficient to satisfy the requirements of the RAMBUS signal channel. Therefore, two memory modules can be vertically stacked to achieve higher memory density and thereby conserve board space.

Abstract translation: 本发明的RAMBUS兼容配置通过以相对于另一个的上下颠倒的方式堆叠在层叠结构中的两个模块之一来实现。 这样，每个存储器模块的相应的电引线将在堆叠封装的相对侧上延伸，并且将牢固地连接到垂直导轨。 垂直导轨电连接到电连接到RAMBUS信号通道的接合焊盘。 在该实施例中，一个存储器模块的电引线在位于堆叠封装的一侧的点处电连接到信号通道，另一存储器模块的电引线在位于该堆叠封装的相对侧上的点处连接到信号通道 堆叠包装。 层叠包装中的每个存储器模块的相应引线之间的所得接触点之间的距离足以满足RAMBUS信号通道的要求。 因此，可以将两个存储器模块垂直堆叠以实现更高的存储器密度，从而节省电路板空间。

公开(公告)号：US07586758B2

公开(公告)日：2009-09-08

申请号：US10958924

申请日：2004-10-05

Applicant: James W. Cady ,  James Wilder ,  David L. Roper ,  Russell Rapport ,  James Douglas Wehrly, Jr. ,  Jeffrey Alan Buchle

Inventor： James W. Cady ,  James Wilder ,  David L. Roper ,  Russell Rapport ,  James Douglas Wehrly, Jr. ,  Jeffrey Alan Buchle

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H01L23/49816 ,  H01L23/3114 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00012

Abstract: The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The present invention can be used to advantage with packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element CSP integrated circuit and a support element CSP integrated circuit are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two CSP elements. A portion of the flex circuit connected to the support element is folded over the base element to dispose the support element above the base element while reducing the overall footprint. The flex circuit provides a thermal and electrical connection path between the module and an application environment such as a printed wiring board (PWB).

Abstract translation: 本发明将封装的集成电路堆叠成节省PWB或其他板表面积的模块。 本发明可以利用各种尺寸和配置的封装，其范围从具有许多触点的较大封装的基底元件到较小的封装，例如诸如DSBGA的裸片尺寸的封装。 在根据本发明设计的优选实施例中，基体元件CSP集成电路和支撑元件CSP集成电路通过具有图案化以选择性地连接两个CSP元件的至少两个导电层的柔性电路聚集。 连接到支撑元件的柔性电路的一部分折叠在基座元件上，以将支撑元件设置在基座元件上方，同时减小了总的占地面积。 柔性电路在模块和诸如印刷电路板（PWB）的应用环境之间提供热和电连接路径。