Invention Application
- Patent Title: Digital clock modulator
- Patent Title (中): 数字时钟调制器
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Application No.: US10909939Application Date: 2004-08-02
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Publication No.: US20050063503A1Publication Date: 2005-03-24
- Inventor: Tapas Nandy
- Applicant: Tapas Nandy
- Applicant Address: IN Uttar Pradesh
- Assignee: STMicroelectronics Pvt. Ltd.
- Current Assignee: STMicroelectronics Pvt. Ltd.
- Current Assignee Address: IN Uttar Pradesh
- Priority: IN949/DEL/2003 20030731
- Main IPC: H03K5/1252
- IPC: H03K5/1252 ; H03K5/13 ; H03K7/04 ; H03K7/06 ; H04B15/04 ; H04L7/00 ; H04L25/00

Abstract:
A digital clock modulator provides a smoothly modulated clock period to reduce emitted electro-magnetic radiation (EMR). The digital clock modulator includes a plurality of delay elements connected in series and receiving as an input an unmodulated clock signal. A multiplexer receives inputs from unequally spaced taps between the delay elements. A control block provides selection inputs to the multiplexer, and receives the unmodulated clock signal from the delay elements. The delay elements include a last delay element providing the unmodulated clock signal to the control block. The last delay element has a predetermined delay for ensuring that the delay elements and related signal paths are in a same stable state before control to the multiplexer changes.
Public/Granted literature
- US07436235B2 Digital clock modulator Public/Granted day:2008-10-14
Information query
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