A real time processor system comprises: a bus arbiter; a plurality of calculating units, each having a processor and an interruption processing unit; a DMA controller; a plurality of priority registers; a memory; and an SCI. The bus arbiter comprises: a priority comparing unit; and a bus assignment unit. Each of the plurality of priority registers stores an I/O access priority value corresponding to each of the calculating units. Priority values are compared, and then right of I/O use is determined. The values of the plurality of priority registers are changed, thereby adaptively performing multiple interruption processing.