Invention Application
US20050066151A1 Method and apparatus for handling predicated instructions in an out-of-order processor
审中-公开
用于处理乱序处理器中的预测指令的方法和装置
- Patent Title: Method and apparatus for handling predicated instructions in an out-of-order processor
- Patent Title (中): 用于处理乱序处理器中的预测指令的方法和装置
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Application No.: US10666343Application Date: 2003-09-19
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Publication No.: US20050066151A1Publication Date: 2005-03-24
- Inventor: Sailesh Kottapalli
- Applicant: Sailesh Kottapalli
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/318 ; G06F9/38
Abstract:
A method and apparatus for permitting out-of-order execution of predicated instructions is disclosed. In one embodiment, a predicated instruction may be decoded into a related predicated instruction and a move instruction contingent on the complementary value of the predicate of the predicated instruction. The destination register of both the related predicated instruction and the move instruction may be mapped to the same physical register, and only one of the two instructions may update machine state with its results.
Information query
