公开(公告)号：US11243770B2

公开(公告)日：2022-02-08

申请号：US15966472

申请日：2018-04-30

申请人： International Business Machines Corporation

发明人： Michael Karl Gschwind ,  Valentina Salapura ,  Chung-Lung K. Shum ,  Timothy J. Slegel

IPC分类号： G06F9/318 ,  G06F9/30 ,  G06F9/46 ,  G06F12/0875 ,  G06F9/38 ,  G06F12/0815 ,  G06F12/0811 ,  G06F12/0831

摘要： An instruction stream includes a transactional code region. The transactional code region includes a latent modification instruction (LMI), a next sequential instruction (NSI) following the LMI, and a set of target instructions following the NSI in program order. Each target instruction has an associated function, and the LMI at least partially specifies a substitute function for the associated function. A processor executes the LMI, the NSI, and at least one of the target instructions, employing the substitute function at least partially specified by the LMI. The LMI, the NSI, and the target instructions may be executed by the processor in sequential program order or out of order.

公开(公告)号：US11010166B2

公开(公告)日：2021-05-18

申请号：US15087854

申请日：2016-03-31

申请人： Intel Corporation

发明人： Debabrata Mohapatra ,  Perry H. Wang ,  Xiang Zou ,  Sang Kyun Kim ,  Deepak A. Mathaikutty ,  Gautham N. Chinya

IPC分类号： G06F9/302 ,  G06F9/318 ,  G06F9/30

摘要： A processor includes a front end including circuitry to decode a first instruction to set a performance register for an execution unit and a second instruction, and an allocator including circuitry to assign the second instruction to the execution unit to execute the second instruction. The execution unit includes circuitry to select between a normal computation and an accelerated computation based on a mode field of the performance register, perform the selected computation, and select between a normal result associated with the normal computation and an accelerated result associated with the accelerated computation based on the mode field.

公开(公告)号：US08892851B2

公开(公告)日：2014-11-18

申请号：US13287412

申请日：2011-11-02

申请人： Adam J. Muff ,  Paul E. Schardt ,  Robert A. Shearer ,  Matthew R. Tubbs

发明人： Adam J. Muff ,  Paul E. Schardt ,  Robert A. Shearer ,  Matthew R. Tubbs

IPC分类号： G06F9/318 ,  G06F9/30

CPC分类号： G06F9/30 ,  G06F9/30145 ,  G06F9/30181 ,  G06F9/3832

摘要： A circuit arrangement and method support compression and expansion of instruction opcodes by detecting successive address targeting and decoding a first opcode of an instruction into a second opcode in response to detecting successive address targeting. The circuit arrangement and method execute instructions in an instruction stream and detect successive address targeting by two or more instructions in the instruction stream without the targeted address being utilized as a source address in an instruction executed between the first and second instructions in the instruction stream. Then, based on that detection, the opcode of the second instruction is modified, changed, or appended to such that a different opcode is indicated by the second instruction, such that executing the second instruction causes a different unique type of operation to be performed.

摘要翻译： 电路布置和方法通过响应于检测到连续的地址目标来检测连续的地址目标和将指令的第一操作码解码成第二操作码来支持指令操作码的压缩和扩展。 电路装置和方法在指令流中执行指令，并且在指令流中的指令流中的第一和第二指令之间执行的指令中，用目标地址作为源地址来检测指令流中两个或多个指令的连续地址定向。 然后，基于该检测，第二指令的操作码被修改，改变或附加，使得由第二指令指示不同的操作码，使得执行第二指令导致执行不同的独特类型的操作。

公开(公告)号：US20130262839A1

公开(公告)日：2013-10-03

申请号：US13432458

申请日：2012-03-28

申请人： Michael K. Gschwind ,  Valentina Salapura

发明人： Michael K. Gschwind ,  Valentina Salapura

IPC分类号： G06F9/30 ,  G06F9/318

CPC分类号： G06F9/30181 ,  G06F9/3017 ,  G06F9/3836

摘要： A computer system for optimizing instructions is configured to identify two or more machine instructions as being eligible for optimization, to merge the two or more machine instructions into a single optimized internal instruction that is configured to perform functions of the two or more machine instructions, and to execute the single optimized internal instruction to perform the functions of the two or more machine instructions. Being eligible includes determining that the two or more machine instructions include a first instruction specifying a first target register and a second instruction specifying the first target register as a source register and a target register. The second instruction is a next sequential instruction of the first instruction in program order, wherein the first instruction specifies a first function to be performed, and the second instruction specifies a second function to be performed.

摘要翻译： 用于优化指令的计算机系统被配置为将两个或更多个机器指令识别为有资格进行优化，以将两个或多个机器指令合并成被配置为执行两个或更多个机器指令的功能的单个优化内部指令，以及 执行单个优化的内部指令来执行两个或更多个机器指令的功能。 合格包括确定两个或多个机器指令包括指定第一目标寄存器的第一指令和指定第一目标寄存器作为源寄存器和目标寄存器的第二指令。 第二指令是程序顺序中的第一指令的下一个顺序指令，其中第一指令指定要执行的第一功能，并且第二指令指定要执行的第二功能。

公开(公告)号：US20130166891A1

公开(公告)日：2013-06-27

申请号：US13041168

申请日：2011-03-04

申请人： Bruce E. Kaskel ,  Paul Holland

发明人： Bruce E. Kaskel ,  Paul Holland

IPC分类号： G06F21/00 ,  G06F9/318

CPC分类号： G06F21/53

摘要： Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for enveloping a thread of execution within an IDT-based secure sandbox. In one aspect, embodiments of the invention provide a method performed in a computer system, the method receiving an instruction from an execution thread where the computer system can be configured for redirection of instructions from the execution thread. The method can determine whether the instruction includes at least one of an interrupt instruction, a system call instruction and a system enter instruction. In response to determining that the instruction includes at least one of the interrupt instruction, the system call instruction and the system enter instruction, the method can further: (i) eliminate the redirection, (ii) modify a stack to specify return of control, and (iii) thereafter, pass the control to an operating system kernel.

摘要翻译： 方法，系统和装置，包括在计算机存储介质上编码的计算机程序，用于在基于IDT的安全沙箱内包围执行线程。 在一个方面，本发明的实施例提供了一种在计算机系统中执行的方法，该方法从执行线程接收指令，其中计算机系统可被配置用于从执行线程重定向指令。 该方法可以确定指令是否包括中断指令，系统调用指令和系统输入指令中的至少一个。 响应于确定指令包括中断指令，系统调用指令和系统输入指令中的至少一个，该方法还可以：（i）消除重定向，（ii）修改堆栈以指定控制返回， 和（iii）之后，将控制权传递给操作系统内核。

公开(公告)号：US08397052B2

公开(公告)日：2013-03-12

申请号：US12543688

申请日：2009-08-19

申请人： Alexandre E. Eichenberger ,  Alan Gara ,  Kathryn M. O'Brien ,  Martin Ohmacht ,  Xiaotong Zhuang

发明人： Alexandre E. Eichenberger ,  Alan Gara ,  Kathryn M. O'Brien ,  Martin Ohmacht ,  Xiaotong Zhuang

IPC分类号： G06F9/318

CPC分类号： G06F9/3851 ,  G06F9/3885 ,  G06F12/0842

摘要： Mechanisms are provided for controlling version pressure on a speculative versioning cache. Raw version pressure data is collected based on one or more threads accessing cache lines of the speculative versioning cache. One or more statistical measures of version pressure are generated based on the collected raw version pressure data. A determination is made as to whether one or more modifications to an operation of a data processing system are to be performed based on the one or more statistical measures of version pressure, the one or more modifications affecting version pressure exerted on the speculative versioning cache. An operation of the data processing system is modified based on the one or more determined modifications, in response to a determination that one or more modifications to the operation of the data processing system are to be performed, to affect the version pressure exerted on the speculative versioning cache.

摘要翻译： 提供了用于控制推测版本缓存的版本压力的机制。 基于访问推测性版本缓存的高速缓存行的一个或多个线程来收集原始版本压力数据。 基于收集的原始版本压力数据生成版本压力的一个或多个统计度量。 确定是否将基于版本压力的一个或多个统计测量来执行对数据处理系统的操作的一个或多个修改，该一个或多个修改影响施加在推测版本缓存上的版本压力。 响应于将要执行对数据处理系统的操作的一个或多个修改以影响施加在投机上的版本压力的确定，基于一个或多个确定的修改来修改数据处理系统的操作 版本缓存。

公开(公告)号：US20120260068A1

公开(公告)日：2012-10-11

申请号：US13416879

申请日：2012-03-09

申请人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker

发明人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker

IPC分类号： G06F9/318

CPC分类号： G06F9/30167 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30112 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/3806

摘要： An ISA-defined instruction includes an immediate field having a first and second portions specifying first and second values, which instructs the microprocessor to perform an operation using a constant value as one of its source operands. The constant value is the first value rotated/shifted by a number of bits based on the second value. An instruction translator translates the instruction into one or more microinstructions. An execution pipeline executes the microinstructions generated by the instruction translator. The instruction translator, rather than the execution pipeline, generates the constant value for the execution pipeline as a source operand of at least one of the microinstructions for execution by the execution pipeline. Alternatively, if the immediate field value is not within a predetermined subset of values known by the instruction translator, the instruction translator generates, rather than the constant, a second microinstruction for execution by the execution pipeline to generate the constant.

摘要翻译： ISA定义的指令包括具有指定第一和第二值的第一和第二部分的立即字段，其指示微处理器使用常数值作为其源操作数之一执行操作。 常数值是基于第二值旋转/移位多个位的第一值。 指令翻译器将指令转换为一个或多个微指令。 执行流水线执行指令转换器生成的微指令。 指令转换器而不是执行流水线，将执行流水线的常量值作为执行流水线执行的至少一个微指令的源操作数。 或者，如果立即字段值不在指令转换器已知的值的预定子集内，则指令转换器生成第二微指令而不是常数，用于由执行流水线执行以产生常数。

公开(公告)号：US08271998B2

公开(公告)日：2012-09-18

申请号：US11741224

申请日：2007-04-27

申请人： Paolo Dettori ,  Julio Nogima ,  Frank Andre Schaffa

发明人： Paolo Dettori ,  Julio Nogima ,  Frank Andre Schaffa

IPC分类号： G06F9/318

CPC分类号： G06F8/36 ,  G06F8/24 ,  G06F8/34

摘要： Exemplary illustrative embodiments provide for a method implemented in a service oriented architecture environment including a plurality of live services. The method includes composing, at runtime, a composed service by mapping a first parameter of a first subset of live services to a second parameter of a second subset of live services. The first subset and the second subset are part of the plurality of live services. The method can further include storing the composed service in a memory.

摘要翻译： 示例性实施例提供了在面向服务的架构环境中实现的包括多个直播服务的方法。 该方法包括在运行时通过将实时服务的第一子集的第一参数映射到实时服务的第二子集的第二参数来组合组合服务。 第一子集和第二子集是多个实时服务的一部分。 该方法还可以包括将组合服务存储在存储器中。

公开(公告)号：US20120216014A1

公开(公告)日：2012-08-23

申请号：US13031915

申请日：2011-02-22

申请人： Michael J. Branson ,  John M. Santosuosso

发明人： Michael J. Branson ,  John M. Santosuosso

IPC分类号： G06F9/318 ,  G06F15/76

CPC分类号： G06F9/52 ,  G06F9/38 ,  G06F9/3851 ,  G06F9/505 ,  G06F11/1683 ,  G06F15/17325 ,  G06F17/30516

摘要： Techniques are described for abating the negative effects of wait conditions in a distributed system by temporarily decreasing the execution time of processing elements. Embodiments of the invention may generally identify wait conditions from an operator graph and detect the slowest processing element preceding the wait condition based on either historical information or real-time data. Once identified, the slowest processing element may be sped up to lessen the negative consequences of the wait condition. Alternatively, if the slowest processing element shares the same compute node with another processing element in the distributed system, one of the processing elements may be transferred to a different compute node to free additional computing resources on the compute node.

摘要翻译： 描述了通过暂时减少处理元件的执行时间来减轻分布式系统中的等待状况的负面影响的技术。 本发明的实施例通常可以从运营商图表中识别等待状况，并且基于历史信息或实时数据来检测等待条件之前的最慢处理元素。 一旦被识别，最慢的处理元件可以加快以减轻等待条件的负面后果。 或者，如果最慢的处理元件与分布式系统中的另一个处理元件共享相同的计算节点，则可以将处理元件之一传送到不同的计算节点以释放计算节点上的附加计算资源。

公开(公告)号：US20120179894A1

公开(公告)日：2012-07-12

申请号：US13419135

申请日：2012-03-13

申请人： Jeroen Anton Johan Leijten ,  Hendrik Tjeerd Joannes Zwartenkot

发明人： Jeroen Anton Johan Leijten ,  Hendrik Tjeerd Joannes Zwartenkot

IPC分类号： G06F9/318 ,  G06F9/315 ,  G06F15/76

CPC分类号： G06F9/30149 ,  G06F8/445 ,  G06F9/30054 ,  G06F9/30138 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/322 ,  G06F9/3816 ,  G06F9/3867

摘要： A data processing circuit is described that includes an instruction decoder operable in a first and a second instruction mode. In the first instruction mode instructions have respective fields for controlling each of multiple functional units, and in the second instruction mode instructions controlling only one functional unit. A mode control circuit controls selecting the instruction modes. The instruction decoder uses time-stationary decoding of operations and destination registers. When instructions are scheduled, constraints are imposed on operations for which operation selection and destination register selection are included on different sides of an instruction mode change. When an instruction containing a jump is encountered, the mode control circuit sets the instruction mode for subsequent instructions in conformity with information provided by executing the jump command.

摘要翻译： 描述了包括可在第一和第二指令模式下操作的指令解码器的数据处理电路。 在第一指令模式中，指令具有用于控制多个功能单元中的每一个的相应字段，并且在第二指令模式指令中仅控制一个功能单元。 模式控制电路控制选择指令模式。 指令解码器使用操作和目标寄存器的时间稳定解码。 当指令被调度时，对指令模式改变的不同侧包括操作选择和目标寄存器选择的操作施加约束。 当遇到包含跳转的指令时，模式控制电路根据通过执行跳转命令提供的信息来设置用于后续指令的指令模式。