The problem of the invention, which concerns a method for arranging circuit elements in semiconductor components, in which according to a circuit draft, using a standard cell library, a physical layout is produced, in which the circuit elements are placed in the layout, one after the other, with their components, and with this layout, the circuit elements are structured in the semiconductor component, wherein each of the circuit elements has a driver, to which a driver strength is established, and connecting elements, is to indicate a method with which a placing of the circuit elements can be undertaken in such a way that a functionally reliable timing can be purposefully attained. This is attained in that the sensitivity of the circuit elements for a parasitic electromagnetic influencing is evaluated and in that the circuit elements with the highest sensitivity—that is, the susceptibility for parasitic influencing—are first placed with the shortest possible connecting elements.