利索-全球专利检索

  1. 登录
  2. 注册
发明申请
US20050067722A1 Semiconductor device which prevents peeling of low-permittivity film by using multilevel interconnection 失效
通过使用多层互连防止低电容率膜的剥离的半导体装置

  • 专利标题： Semiconductor device which prevents peeling of low-permittivity film by using multilevel interconnection
  • 专利标题（中）： 通过使用多层互连防止低电容率膜的剥离的半导体装置
  • 申请号： US10731148
    申请日： 2003-12-10
  • 公开(公告)号： US20050067722A1
    公开(公告)日： 2005-03-31
  • 发明人: Hidetoshi Koike
  • 申请人： Hidetoshi Koike
  • 优先权： JP2003-340588 20030930
  • 主分类号： H01L23/52
  • IPC分类号： H01L23/52 ;  H01L21/3205 ;  H01L23/544
Semiconductor device which prevents peeling of low-permittivity film by using multilevel interconnection
摘要：
A semiconductor device includes an alignment mark which is arranged adjacent to each corner of a semiconductor chip, and a plug which contacts the alignment mark. The alignment mark is formed by part of the uppermost interconnection layer in a multilevel interconnection which is formed on the semiconductor chip and obtained by stacking low-permittivity insulating layers and interconnection layers. The plug is buried in a contact hole formed in the low-permittivity insulating layer below the alignment mark, and contacts the alignment mark.
摘要（中）：

半导体器件包括与半导体芯片的每个角相邻配置的对准标记和与对准标记接触的插头。 在半导体芯片中形成的多层互连中的最上层布线层的一部分形成对准标记，并且通过层叠低介电常数绝缘层和互连层而得到。 插头埋在形成在对准标记下方的低介电常数绝缘层中的接触孔中，并接触对准标记。

公开/授权文献
信息查询
Global Dossier Espacenet
0/0