公开(公告)号：US20120299071A1

公开(公告)日：2012-11-29

申请号：US13423382

申请日：2012-03-19

申请人： Hidetoshi KOIKE

发明人： Hidetoshi KOIKE

IPC分类号： H01L31/0224

CPC分类号： H01L27/14643 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/14616 ,  H01L27/14689

摘要： According to one embodiment, a solid-state imaging device includes a photodiode includes an N-type region and a P-type region, a floating diffusion region, and a transfer transistor. The N-type diffusion region of the photodiode comprises a first semiconductor region and a second semiconductor region formed shallower than the first semiconductor region. An end portion of the first semiconductor region is positioned on the floating diffusion region side rather than an end portion of a gate electrode of the transfer transistor. An end portion of the second semiconductor region is set in substantially the same position as that of the end portion of the gate electrode of the transfer transistor.

摘要翻译： 根据一个实施例，固态成像装置包括光电二极管，包括N型区域和P型区域，浮动扩散区域和转移晶体管。 光电二极管的N型扩散区域包括形成为比第一半导体区域浅的第一半导体区域和第二半导体区域。 第一半导体区域的端部位于浮动扩散区域侧，而不是转移晶体管的栅电极的端部。 第二半导体区域的端部设置在与转移晶体管的栅电极的端部大致相同的位置。

公开(公告)号：US20120068293A1

公开(公告)日：2012-03-22

申请号：US13308621

申请日：2011-12-01

申请人： Hidetoshi KOIKE

发明人： Hidetoshi KOIKE

IPC分类号： H01L31/0232

CPC分类号： H01L27/14623 ,  H01L27/14627 ,  H01L27/14685

摘要： A pixel area for generating an image signal corresponding to incident light is formed on a semiconductor substrate. A light-shielding layer is formed on the semiconductor substrate around the pixel area. The light-shielding layer has a slit near the pixel area and shields the incident light. A passivation film is formed in the pixel area, on the light-shielding layer, and in the slit. A coating layer is formed in the slit of the light-shielding layer and on the passivation film in the pixel area. Microlenses are formed on the coating layer in the pixel area.

摘要翻译： 在半导体基板上形成用于产生与入射光对应的图像信号的像素区域。 在像素区域周围的半导体基板上形成遮光层。 遮光层在像素区域附近具有狭缝，并遮蔽入射光。 在像素区域，遮光层和狭缝中形成钝化膜。 在遮光层的狭缝和像素区域中的钝化膜上形成涂层。 在像素区域的涂层上形成微透镜。

公开(公告)号：US20100301444A1

公开(公告)日：2010-12-02

申请号：US12725511

申请日：2010-03-17

申请人： Hidetoshi KOIKE

发明人： Hidetoshi KOIKE

IPC分类号： H01L31/02 ,  H01L31/18

CPC分类号： H01L27/14636 ,  H01L27/14687

摘要： Photoelectric conversion elements are arranged in a pixel area. A circuit area is arranged around the pixel area. An interconnect including copper is arranged in the pixel area and circuit area. A cap layer is arranged on the interconnect. Wherein the cap layer except a part on the interconnect is removed from the pixel area and circuit area.

摘要翻译： 光电转换元件被布置在像素区域中。 电路区域围绕像素区域布置。 包括铜的互连被布置在像素区域和电路区域中。 互连上布置有盖层。 其中除了互连上的部分之外的覆盖层从像素区域和电路区域中去除。

公开(公告)号：US20080283948A1

公开(公告)日：2008-11-20

申请号：US12119689

申请日：2008-05-13

申请人： Hidetoshi KOIKE

发明人： Hidetoshi KOIKE

IPC分类号： H01L31/0216 ,  H01L21/04

CPC分类号： H01L27/14623 ,  H01L27/14627 ,  H01L27/14685

摘要： A pixel area for generating an image signal corresponding to incident light is formed on a semiconductor substrate. A light-shielding layer is formed on the semiconductor substrate around the pixel area. The light-shielding layer has a slit near the pixel area and shields the incident light. A passivation film is formed in the pixel area, on the light-shielding layer, and in the slit. A coating layer is formed in the slit of the light-shielding layer and on the passivation film in the pixel area. Microlenses are formed on the coating layer in the pixel area.

摘要翻译： 在半导体基板上形成用于产生与入射光对应的图像信号的像素区域。 在像素区域周围的半导体基板上形成遮光层。 遮光层在像素区域附近具有狭缝，并遮蔽入射光。 在像素区域，遮光层和狭缝中形成钝化膜。 在遮光层的狭缝和像素区域中的钝化膜上形成涂层。 在像素区域的涂层上形成微透镜。

公开(公告)号：US07268068B2

公开(公告)日：2007-09-11

申请号：US11078031

申请日：2005-03-11

申请人： Hidetoshi Koike

发明人： Hidetoshi Koike

IPC分类号： H01L21/4763 ,  H01L21/82 ,  H01L21/44 ,  H01L21/8238 ,  H01L21/326

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprises a multiple insulation layer structure in which multiple insulation layers each having interconnection layer are built up and either one of the interconnection layer forming a fuse is blown in order to select a spare cell to relieve a defective cell; and an opening area corresponding to said fuse, the opening being formed on one or more insulation layers disposed above the layer which includes the fuse, wherein a side wall position corresponding to the opening of the first protective insulation film formed on the top layer of the multiple layers and a side wall position corresponding to the opening of the second protective insulation film formed on the first protective insulation film are continuous at the boundary thereof.

摘要翻译： 一种半导体器件包括多层绝缘层结构，其中构成具有互连层的多个绝缘层，并且形成形成熔丝的互连层中的任一个被熔断以选择备用电池以减轻有缺陷的电池; 以及对应于所述保险丝的开口区域，所述开口形成在设置在包括所述保险丝的所述层之上的一个或多个绝缘层上，其中对应于形成在所述保险丝的顶层上的所述第一保护绝缘膜的开口的侧壁位置 与第一保护绝缘膜上形成的第二保护绝缘膜的开口相对应的多层和侧壁位置在其边界处是连续的。

公开(公告)号：US20070170544A1

公开(公告)日：2007-07-26

申请号：US11624809

申请日：2007-01-19

申请人： Hidetoshi Koike

发明人： Hidetoshi Koike

IPC分类号： H01L29/00

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A trench dummy element isolating region is formed in the fuse region of a semiconductor substrate. In the semiconductor substrate, a plurality of dummy element regions is formed so as to be enclosed by the trench dummy element isolating region. The occupancy rate of the plurality of dummy element regions in the fuse region is equal to or larger than a specific value. On the semiconductor substrate including the dummy element isolating region and dummy element regions, a plurality of metal fuses composed of multilayer metal wiring lines are formed via an interlayer insulating film. The plurality of dummy element regions are formed only below at least a part of the plurality of metal fuses.

摘要翻译： 沟槽虚设元件隔离区域形成在半导体衬底的熔丝区域中。 在半导体衬底中，多个虚设元件区被形成为被沟槽虚设元件隔离区包围。 熔丝区域中的多个虚设元件区域的占有率等于或大于特定值。 在具有虚拟元件隔离区域和虚设元件区域的半导体基板上，经由层间绝缘膜形成由多层金属布线构成的多个金属熔丝。 多个虚设元件区域仅形成在多个金属保险丝的至少一部分的下方。

公开(公告)号：US07205636B2

公开(公告)日：2007-04-17

申请号：US11437656

申请日：2006-05-22

申请人： Hidetoshi Koike

发明人： Hidetoshi Koike

IPC分类号： H01L23/544 ,  H01L21/46

CPC分类号： H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes an alignment mark which is arranged adjacent to each corner of a semiconductor chip, and a plug which contacts the alignment mark. The alignment mark is formed by part of the uppermost interconnection layer in a multilevel interconnection which is formed on the semiconductor chip and obtained by stacking low-permittivity insulating layers and interconnection layers. The plug is buried in a contact hole formed in the low-permittivity insulating layer below the alignment mark, and contacts the alignment mark.

摘要翻译： 半导体器件包括与半导体芯片的每个角相邻配置的对准标记和与对准标记接触的插头。 在半导体芯片中形成的多层互连中的最上层布线层的一部分形成对准标记，并且通过层叠低介电常数绝缘层和互连层而得到。 插头埋在形成在对准标记下方的低介电常数绝缘层中的接触孔中，并接触对准标记。

公开(公告)号：US06989560B2

公开(公告)日：2006-01-24

申请号：US10676123

申请日：2003-10-02

申请人： Hidetoshi Koike ,  Tomoya Sanuki

发明人： Hidetoshi Koike ,  Tomoya Sanuki

IPC分类号： H01L27/108 ,  H01L21/8239 ,  G11C11/24

CPC分类号： H01L27/10867 ,  H01L27/0207 ,  H01L27/10829 ,  H01L27/10864 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/66181 ,  H01L29/945

摘要： Since at least a portion of a trench capacitor electrode is formed by a metal, the electrical sheet resistance of the electrode can be lowered, and the signal propagation time prolonged by CR delay can be shortened. This can reduce the read/write time. The formation of a buried gate electrode can realize a reduction of the cell area, which is required in a DRAM- and a DRAM/logic-embedded device. This can increase the gate length and reduce the short channel effect. Since an insulating protective film is deposited on the gate electrode, a bit line contact can be formed in self-alignment.

公开(公告)号：US20050067722A1

公开(公告)日：2005-03-31

申请号：US10731148

申请日：2003-12-10

申请人： Hidetoshi Koike

发明人： Hidetoshi Koike

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L23/544

CPC分类号： H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes an alignment mark which is arranged adjacent to each corner of a semiconductor chip, and a plug which contacts the alignment mark. The alignment mark is formed by part of the uppermost interconnection layer in a multilevel interconnection which is formed on the semiconductor chip and obtained by stacking low-permittivity insulating layers and interconnection layers. The plug is buried in a contact hole formed in the low-permittivity insulating layer below the alignment mark, and contacts the alignment mark.

摘要翻译： 半导体器件包括与半导体芯片的每个角相邻配置的对准标记和与对准标记接触的插头。 在半导体芯片中形成的多层互连中的最上层布线层的一部分形成对准标记，并且通过层叠低介电常数绝缘层和互连层而得到。 插头埋在形成在对准标记下方的低介电常数绝缘层中的接触孔中，并接触对准标记。

公开(公告)号：US08399946B1

公开(公告)日：2013-03-19

申请号：US13659483

申请日：2012-10-24

申请人： Hidetoshi Koike

发明人： Hidetoshi Koike

IPC分类号： H01L31/0232

CPC分类号： H01L27/1463 ,  H01L27/14627 ,  H01L27/14643 ,  H01L27/14689 ,  H04N5/335

摘要： According to one embodiment, a solid-state imaging device includes a semiconductor substrate of a first conductive type having a diffusion layer region provided on a surface thereof, a diffusion layer of the first conductive type for a pixel separation whose bottom portion is formed at the deepest position of the diffusion layer region in a pixel region, and a first deep diffusion layer of the first conductive type provided at the deepest position of the diffusion layer region in a first peripheral logic region for electrically connecting the semiconductor substrate and the first peripheral logic region and having a first concentration gradient equal to that of the diffusion layer for pixel separation.

摘要翻译： 根据一个实施例，固态成像装置包括：第一导电类型的半导体衬底，其具有设置在其表面上的扩散层区域;第一导电类型的扩散层，用于像素分离，其底部形成在 在第一外围逻辑区域中设置在扩散层区域的最深位置处的第一导电类型的第一深度扩散层，用于将半导体衬底和第一外围逻辑电连接 并且具有与用于像素分离的扩散层的第一浓度梯度相等的第一浓度梯度。