发明申请
US20050078543A1 DUAL-PORTED READ SRAM CELL WITH IMPROVED SOFT ERROR IMMUNITY
失效
双重读取SRAM单元,具有改进的软错误免疫
- 专利标题: DUAL-PORTED READ SRAM CELL WITH IMPROVED SOFT ERROR IMMUNITY
- 专利标题(中): 双重读取SRAM单元,具有改进的软错误免疫
-
申请号: US10684019申请日: 2003-10-10
-
公开(公告)号: US20050078543A1公开(公告)日: 2005-04-14
- 发明人: Reid Riedlinger , Brandon Yelton , Steven Affleck
- 申请人: Reid Riedlinger , Brandon Yelton , Steven Affleck
- 主分类号: G11C11/41
- IPC分类号: G11C11/41 ; G11C8/16 ; G11C11/412 ; G11C8/00
摘要:
In a preferred embodiment, the invention provides a circuit and method for improving the soft error rate in a dual-port read SRAM cell. A write-only transfer device is connected to a cross-coupled latch, a first wordline, and a first bitline. A first read-only transfer device is connected to a second bitline, a second wordline, and a first pull-down device. A second read-only transfer device is connected to the first bitline, the first wordline, and a second pull-down device. A clear memory transfer device is connected to the cross-coupled latch, a third bitline, and a third pull-down device. This configuration allows a reduction in the size of a dual-port SRAM cell with little or no reduction in the read access time of the cell. The reduction in size also reduces SER by reducing the cross-sectional, p/n junction area exposed to radiation.
公开/授权文献
信息查询