公开(公告)号：US20050078543A1

公开(公告)日：2005-04-14

申请号：US10684019

申请日：2003-10-10

申请人： Reid Riedlinger ,  Brandon Yelton ,  Steven Affleck

发明人： Reid Riedlinger ,  Brandon Yelton ,  Steven Affleck

IPC分类号： G11C11/41 ,  G11C8/16 ,  G11C11/412 ,  G11C8/00

CPC分类号： G11C11/4125 ,  G11C8/16

摘要： In a preferred embodiment, the invention provides a circuit and method for improving the soft error rate in a dual-port read SRAM cell. A write-only transfer device is connected to a cross-coupled latch, a first wordline, and a first bitline. A first read-only transfer device is connected to a second bitline, a second wordline, and a first pull-down device. A second read-only transfer device is connected to the first bitline, the first wordline, and a second pull-down device. A clear memory transfer device is connected to the cross-coupled latch, a third bitline, and a third pull-down device. This configuration allows a reduction in the size of a dual-port SRAM cell with little or no reduction in the read access time of the cell. The reduction in size also reduces SER by reducing the cross-sectional, p/n junction area exposed to radiation.

摘要翻译： 在优选实施例中，本发明提供了一种用于改善双端口读SRAM单元中的软错误率的电路和方法。 只写传输设备连接到交叉耦合锁存器，第一字线和第一位线。 第一只读传送装置连接到第二位线，第二字线和第一下拉装置。 第二只读传送设备连接到第一位线，第一字线和第二下拉设备。 清晰的存储器传输装置连接到交叉耦合的锁存器，第三位线和第三下拉器件。 这种配置允许在单元的读取访问时间几乎或不减少的情况下减小双端口SRAM单元的尺寸。 通过减少暴露于辐射的横截面的p / n结面积，尺寸的减小也降低了SER。

公开(公告)号：US20060055428A1

公开(公告)日：2006-03-16

申请号：US10940703

申请日：2004-09-14

申请人： Steven Affleck ,  Reid Riedlinger ,  Douglas Stirrett

发明人： Steven Affleck ,  Reid Riedlinger ,  Douglas Stirrett

IPC分类号： H03K19/096

CPC分类号： G06F17/5045 ,  H03K19/0963

摘要： One disclosed embodiment may comprise a design method for a dynamic circuit system. The method may include providing a design for a single stage network comprising a pull-down network that is configured to perform a desired logic function according to a plurality of inputs. The method may also include designing a multi-stage network that includes at least two stages, each of the at least two stages including a pull-down network that receives a respective portion of the plurality of inputs and each of the at least two stages cooperating to perform the desired logic function.

摘要翻译： 一个公开的实施例可以包括用于动态电路系统的设计方法。 该方法可以包括提供用于单级网络的设计，其包括被配置为根据多个输入执行期望的逻辑功能的下拉网络。 该方法还可以包括设计包括至少两个级的多级网络，所述至少两个级中的每一级包括接收所述多个输入的相应部分的下拉网络，并且所述至少两个阶段中的每一个协作 执行所需的逻辑功能。