Invention Application
US20050083099A1 Capture clock generator using master and slave delay locked loops
审中-公开
捕获时钟发生器使用主和从延迟锁定环路
- Patent Title: Capture clock generator using master and slave delay locked loops
- Patent Title (中): 捕获时钟发生器使用主和从延迟锁定环路
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Application No.: US11003144Application Date: 2004-12-03
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Publication No.: US20050083099A1Publication Date: 2005-04-21
- Inventor: Feng Lin
- Applicant: Feng Lin
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Main IPC: G11C7/10
- IPC: G11C7/10 ; G11C7/22 ; H03L7/07 ; H03L7/081 ; H04L7/02 ; H03K3/00
Abstract:
A clock generator comprises a master delay locked loop (DLL) and a slave DLL to capture a data signal. The slave DLL generates a slave output signal based on a clock signal. The master DLL receives the slave output signal and compensates variations in delays of the data and clock signals to generate a capture clock signal. When the master and slave DLLs are locked, the capture clock signal is center aligned with the data signal.
Information query
