Invention Application
US20050093075A1 Advanced technique for forming a transistor having raised drain and source regions 失效
用于形成具有升高的漏极和源极区域的晶体管的先进技术

  • Patent Title: Advanced technique for forming a transistor having raised drain and source regions
  • Patent Title (中): 用于形成具有升高的漏极和源极区域的晶体管的先进技术
  • Application No.: US10974232
    Application Date: 2004-10-27
  • Publication No.: US20050093075A1
    Publication Date: 2005-05-05
  • Inventor: Ralf BentumScott LuningAndy Wei
  • Applicant: Ralf BentumScott LuningAndy Wei
  • Priority: DE10351039.7 20031031; DE10351237.3 20031103
  • Main IPC: H01L21/336
  • IPC: H01L21/336 H01L29/76 H01L29/786
Advanced technique for forming a transistor having raised drain and source regions
Abstract:
By recessing a semiconductor layer, preferably by locally oxidizing the semiconductor layer, a stress-inducing material and/or a dopant species may be introduced into the thinned semiconductor layer in the vicinity of a gate electrode structure by means of a subsequent epitaxial growth process. In particular, the stress-inducing material formed adjacent to the gate electrode structure exerts compressive or tensile stress, depending on the type of material deposited, thereby also enhancing the mobility of the charge carriers in a channel region of the transistor element.
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