An apparatus comprising an input circuit, a storage circuit and an output circuit. The input circuit may be configured to generate a plurality of data paths in response to an input data signal having a plurality of data items sequentially presented in a first order. The storage circuit may be configured to store each of the data paths in a respective shift register chain. The output circuit may be configured to generate an output data signal in response to each of the shift register chains. The output data signal presents the data items in a second order different from said first order.