公开(公告)号：US20230070366A1

公开(公告)日：2023-03-09

申请号：US17704864

申请日：2022-03-25

申请人： Hughes Network Systems, LLC

发明人： Jack Edwin Lundstedt, JR. ,  Kumud Patel ,  Walter Kepley

IPC分类号： H04B1/00 ,  H04J3/04

摘要： In some implementations, a communication device, includes a printed circuit board comprising conductors routed to support a plurality of different configurations of modulation and/or demodulation functionality. The printed circuit board can have multiple analog output interfaces and one or more analog input interfaces, multiple digital network interfaces, and sockets for components including a controller, multiple processors, digital-to-analog converters (DACs), and an analog-to-digital converter (ADC). Various processor sockets are interconnected to support the processors in different sockets selectively being used for different functions, e.g., as a modulator, burst processor, channelizer, etc.

公开(公告)号：US11223469B2

公开(公告)日：2022-01-11

申请号：US16686030

申请日：2019-11-15

申请人： Synopsys, Inc.

发明人： Biman Chattopadhyay ,  Ravi Mehta

IPC分类号： H04L7/06 ,  H04L12/863 ,  H03M9/00 ,  H04J3/04 ,  H04J3/06

摘要： A system for serializing input data signals and generating an output data signal includes a FIFO memory that launches the input data signals at different phases of a clock signal. The system further includes multiple stages of a serializer circuit, and each stage of the serializer circuit receives a clock signal. Each successive stage includes half the number of serializer circuits that are included in the previous stage, and each successive stage is clocked by a clock signal that transitions at twice the frequency of the previous stage clock signal. The serializer circuits that belong to a single stage receive the clock signal with different phase. The phase and frequency of clock signals of serializer stages are adjusted such that a launched input data signal is outputted as the output data signal. Further, a critical path for each serializer circuit is equal to full clock cycle of the clock signal.

公开(公告)号：US20200136609A1

公开(公告)日：2020-04-30

申请号：US16660136

申请日：2019-10-22

申请人： LONTIUM SEMICONDUCTOR CORPORATION

发明人： Cheng TAO ,  Hongfeng XIA ,  Yu CHEN ,  Xiangyu JI ,  Jiaxi FU

IPC分类号： H03K17/62 ,  H03K17/687 ,  H04J3/04

摘要： A switch circuit and a high-speed multiplexer-demultiplexer are provided. The switch circuit includes an equalization module and an MOS transistor. A gate of the first MOS transistor is connected to an output terminal of the equalization module. An input terminal of the first MOS transistor is connected to a signal source. An output terminal of the first MOS transistor is connected to a subsequent circuit. The equalization module is configured to: supply a turning-on signal to the first MOS transistor in a case that an operation signal is acquired, to turn on the first MOS transistor; and generate a compensation signal for compensating an attenuation of the signal transmitted through the first MOS transistor, and apply the compensation signal to the gate of the first MOS transistor. The switch circuit operates in response to the operation signal.

公开(公告)号：US10574498B2

公开(公告)日：2020-02-25

申请号：US16264629

申请日：2019-01-31

申请人： Matsing, Inc.

发明人： Serguei Matitsine ,  Igor Timofeev ,  Leonid Matytsine ,  Anthony DeMarco

IPC分类号： H04J3/04 ,  H04L27/26 ,  H01Q1/22 ,  H01Q3/14 ,  H01Q3/24 ,  H01Q3/30 ,  H01Q19/06 ,  H01Q25/00 ,  H01Q1/24

摘要： This application proposes multi-beam antenna systems using spherical lens are proposed, with high isolation between antenna ports and compatible to 2×2, 4×4, 8×8 MIMO transceivers. Several compact multi-band multi-beam solutions (with wideband operation, 40%+, in each band) are achieved by creating dual-band radiators movable on the track around spherical lens and by placing of lower band radiators between spherical lenses. By using of secondary lens for high band radiators, coupling between low band and high band radiators is reduced. Beam tilt range and side lobe suppression are improved by special selection of phase shift and rotational angle of radiators. Resultantly, a wide beam tilt range (0-40 degree) is realized in proposed multi-beam antenna systems. Each beam can be individually tilted. Based on proposed single- and multi-lens antenna solutions, cell coverage improvements and stadium tribune coverage optimization are also achieved, together with interference reduction.

公开(公告)号：US10257795B2

公开(公告)日：2019-04-09

申请号：US14723825

申请日：2015-05-28

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Koji Akita ,  Yukako Tsutsumi ,  Hidenori Okuni

IPC分类号： H04J3/06 ,  H04W56/00 ,  H03M9/00 ,  H04J3/04

摘要： According to an embodiment, a signal conversion apparatus includes a control information generator and a selector. The control information generator generates first control information based on rate information indicating transmission rates of original signals. The first control information designates a first timing at which each of the original signals is sampled. The selector selects each of the sampled signals at a timing based on the first timing. The original signal group includes a first original signal at a first transmission rate and a second original signal at a second transmission rate. The first transmission rate is higher than the second transmission rate. The frequency of allocating the first timing to the first original signal is higher than a frequency of allocating the first timing to the second original signal.

公开(公告)号：US10110334B2

公开(公告)日：2018-10-23

申请号：US15137187

申请日：2016-04-25

申请人： APPLIED MICRO CIRCUITS CORPORATION

发明人： Vijay Gupta ,  Tarun Gupta

IPC分类号： H04J3/06 ,  H04L7/00 ,  H03M9/00 ,  H04J3/04

摘要： Techniques efficiently serialize multiple data streams using quadrature clocks. Serializer employs first, second, third, and fourth clock signals. Serializer receives multiple data streams via registers, with each of four paths comprising a register, buffer, and switch, with registers of first and fourth paths associated with third clock signal, and registers of second and third paths associated with first clock signal, and with switches of first and fourth paths associated with first clock signal, and switches of second and third paths associated with third clock signal. Switches of first and second paths transfer respective data bits to fifth switch via another buffer, wherein fifth switch is associated with a delayed second clock signal of a time delay component (TDC). Switches of third and fourth paths transfer respective data bits to sixth switch via another buffer, wherein sixth switch is associated with a delayed fourth clock signal of TDC.

公开(公告)号：US10027600B2

公开(公告)日：2018-07-17

申请号：US14482295

申请日：2014-09-10

申请人： Artesyn Embedded Computing, Inc.

发明人： Stephan Kruecker ,  Armin Jacht ,  Reinhold Hofer

IPC分类号： H04L12/933 ,  H04J3/04 ,  H04Q11/08 ,  H04J3/16

摘要： A digital signal interface includes a multiplexer coupled to receive a plurality of data signals from at least one of a microprocessor, a microcontroller, or a field-programmable gate array (FPGA), the multiplexer multiplexing the plurality of data signals. The interface further includes a serializer/deserializer (SerDes) transceiver coupled to receive the multiplexed data signals, the SerDes transceiver serializing the multiplexed data signals and transmitting the serialized data signals.

公开(公告)号：US09965520B2

公开(公告)日：2018-05-08

申请号：US13162973

申请日：2011-06-17

申请人： Badrish Chandramouli ,  David E. Maier ,  Jonathan D. Goldstein ,  Peter A. Zabback

发明人： Badrish Chandramouli ,  David E. Maier ,  Jonathan D. Goldstein ,  Peter A. Zabback

IPC分类号： H04J3/04 ,  G06F17/30 ,  G06F9/46 ,  G06F7/00

CPC分类号： G06F17/30516 ,  G06F7/00 ,  G06F9/46

摘要： A logical merge module is described herein for producing an output stream which is logically compatible with two or more physically divergent input streams. Representative applications of the logical merge module are also set forth herein.

公开(公告)号：US09843538B2

公开(公告)日：2017-12-12

申请号：US14599411

申请日：2015-01-16

申请人： BROADCOM CORPORATION

发明人： William Calvin Woodruff

IPC分类号： H04L12/935 ,  H04J3/04 ,  H04J3/06 ,  H04L12/741 ,  H04L12/931

CPC分类号： H04L49/30 ,  H04J3/047 ,  H04J3/0697 ,  H04L45/745 ,  H04L49/40

摘要： A multi-chip module (MCM) may include a substrate, and first and second physical-layer (PHY) chips mounted on the substrate. In some implementations, the first PHY chip includes a multiplexer and a PHY circuit. The multiplexer is configured to receive a multiplexed data stream from a media access control (MAC) device, to demultiplex the multiplexed data stream into first and second data streams, to output the first data stream to the PHY circuit, and to output the second data stream to the second PHY chip. In some implementations, the first PHY includes a router and a PHY circuit. The router is configured to receive a plurality of data packets from a MAC device, to route one or more of the data packets having a first address to the PHY circuit, and to route one or more of the data packets having a second address to the second PHY chip.

公开(公告)号：US09800329B2

公开(公告)日：2017-10-24

申请号：US15171452

申请日：2016-06-02

申请人： FUJITSU LIMITED

发明人： Hironori Hibino

IPC分类号： H04B10/079 ,  H04B10/27 ,  H04B10/29 ,  H04J3/07 ,  H04J3/04 ,  H04B10/077

CPC分类号： H04B10/0771

摘要： An optical network system includes: a plurality of optical transmission devices, each includes a transmitting unit configured to superimpose, on a main signal to be transmitted, a monitoring signal of a different wavelength from wavelengths of other optical transmission devices, the wavelength differing from wavelengths for other optical transmission devices in the optical network system, and an extraction unit configured to extract monitoring signals from main signals received from the other optical transmission devices, wherein a failure occurrence section where a communication failure occurs is determined, based on the monitoring signals extracted by the extraction unit, among transmission sections between the respective optical transmission devices.