Invention Application
US20050097305A1 Method and apparatus for using FPGA technology with a microprocessor for reconfigurable, instruction level hardware acceleration
有权
使用FPGA技术与微处理器进行可重配置,指令级硬件加速的方法和装置
- Patent Title: Method and apparatus for using FPGA technology with a microprocessor for reconfigurable, instruction level hardware acceleration
- Patent Title (中): 使用FPGA技术与微处理器进行可重配置,指令级硬件加速的方法和装置
-
Application No.: US10696865Application Date: 2003-10-30
-
Publication No.: US20050097305A1Publication Date: 2005-05-05
- Inventor: Andreas Doering , Silvio Dragone , Andreas Herkersdorf , Richard Hofmann , Charles Kuhlmann
- Applicant: Andreas Doering , Silvio Dragone , Andreas Herkersdorf , Richard Hofmann , Charles Kuhlmann
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Main IPC: G06F9/00
- IPC: G06F9/00 ; G06F9/318 ; G06F9/38 ; G06F15/78

Abstract:
A method for dynamically programming Field Programmable Gate Arrays (FPGA) in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable “on the fly”, i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising the coprocessor and processor are provided as well.
Public/Granted literature
Information query