发明申请
US20050102597A1 Architecture for an iterative decoder 失效
迭代解码器的架构

Architecture for an iterative decoder
摘要:
Iterative decoder comprising a plurality of servers which perform the iterative decoding of a data block each, an input buffer memory and a control unit which performs a statistical multiplexing of the data at input, which are firstly stored in the input buffer memory and successively processed by one of the servers. The input buffer memory comprises N+L memory locations, where N is the number of servers and L is the number of so-called additional locations. Each block to be decoded which is received while all the servers are busy is stored in one of the L additional locations possibly available, or it is lost if the input buffer memory is entirely filled. The number L of additional locations and the number N of servers are such that the probability PB of a block being lost, calculated on the basis of a queuing model of D/G/N/N+L type, satisfies the condition PB≦α·FER*, where FER* is the error rate in the blocks allowed and α
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