发明申请
US20050116337A1 Method of making multichip wafer level packages and computing systems incorporating same
有权
制造多芯片晶片级封装的方法及其结合的计算系统
- 专利标题: Method of making multichip wafer level packages and computing systems incorporating same
- 专利标题(中): 制造多芯片晶片级封装的方法及其结合的计算系统
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申请号: US11028374申请日: 2005-01-03
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公开(公告)号: US20050116337A1公开(公告)日: 2005-06-02
- 发明人: Swee Kwang Chua , Siu Waf Low , Yong Poo Chia , Meow Koon Eng , Yong Loo Neo , Suan Jeung Boon , Shuangwu Huang , Wei Zhou
- 申请人: Swee Kwang Chua , Siu Waf Low , Yong Poo Chia , Meow Koon Eng , Yong Loo Neo , Suan Jeung Boon , Shuangwu Huang , Wei Zhou
- 主分类号: H01L21/60
- IPC分类号: H01L21/60 ; H01L23/498 ; H01L23/538 ; H01L23/02 ; H01L21/44 ; H01L21/48 ; H01L21/50 ; H01L23/34
摘要:
The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the substrate cavities receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the substrate's back surface is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with their active surface facing up wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice. Computing systems incorporating the packaging are also disclosed.
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