发明申请
- 专利标题: Optimization of critical dimensions and pitch of patterned features in and above a substrate
- 专利标题(中): 优化衬底中和图案上的图案特征的临界尺寸和间距
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申请号: US10728437申请日: 2003-12-05
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公开(公告)号: US20050121790A1公开(公告)日: 2005-06-09
- 发明人: James Cleeves , Roy Scheuerlein
- 申请人: James Cleeves , Roy Scheuerlein
- 申请人地址: US CA Santa Clara
- 专利权人: Matrix Semiconductor, Inc.
- 当前专利权人: Matrix Semiconductor, Inc.
- 当前专利权人地址: US CA Santa Clara
- 主分类号: H01L23/528
- IPC分类号: H01L23/528 ; H01L27/105 ; H01L23/48 ; H01L23/52 ; H01L29/76 ; H01L31/113
摘要:
A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention provides for a memory array formed above a substrate, with driver circuitry formed in the substrate. A level of the memory array consists of, for example, parallel rails and a fan-out region. It is desirable to maximize density of the rails and minimize cost of lithography for the entire memory array. This can be achieved by forming the rails at a tighter pitch than the CMOS circuitry beneath it, allowing cheaper lithography tools to be used when forming the CMOS, and similarly by optimizing lithography and etch techniques for a device level to produce a tight pitch in the rails, and a more relaxed pitch in the less-critical fan-out region.
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