A delayed locked loop in a semiconductor memory device includes a read enable signal generating block for generating a read enable signal, wherein the read enable signal is enabled based on the application of a read command, and is disabled when all data is read out and outputted; a first internal clock controlling block for intermitting the output of a first internal clock through the use of the read enable signal; a second internal clock controlling block for intermitting the output of a second internal clock through the use of the read enable signal; a DLL clock generating block for receiving the first and second internal clocks to thereby generate first and second DLL clocks.